Hardware implementation of Block GC3 lossless compression algorithm for direct-write lithography systems

Hsin-I Liu; Brian Richards; Avideh Zakhor; Borivoje Nikolic

doi:10.1117/12.846447

2 April 2010 Hardware implementation of Block GC3 lossless compression algorithm for direct-write lithography systems

Hsin-I Liu, Brian Richards, Avideh Zakhor, Borivoje Nikolic

Proceedings Volume 7637, Alternative Lithographic Technologies II; 763716 (2010) https://doi.org/10.1117/12.846447
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

Future lithography systems must produce chips with smaller feature sizes, while maintaining throughput comparable to today's optical lithography systems. This places stringent data handling requirements on the design of any direct-write maskless system. To achieve the throughput of one wafer layer per minute with a direct-write maskless lithography system, using 22 nm pixels for 45 nm technology, a data rate of 12 Tb/s is required. In our past research, we have developed a datapath architecture for direct-write lithography systems, and have shown that lossless compression plays a key role in reducing throughput requirements of such systems. Our approach integrates a low complexity hardware-based decoder with the writers, in order to decode a compressed data layer in real time on the fly. In doing so, we have developed a spectrum of lossless compression algorithms for integrated circuit rasterized layout data to provide a tradeoff between compression efficiency and hardware complexity, the most promising of which is Block Golomb Context Copy Coding (Block GC3). In this paper, we present the synthesis results of the Block GC3 decoder for both FPGA and ASIC implementations. For one Block GC3 decoder, 3233 slice flip-flops and 3086 4-input LUTs are utilized in a Xilinx Virtex II Pro 70 FPGA, which corresponds to 4% of its resources, along with 1.7 KB of internal memory. The system runs at 100 MHz clock rate, with the overall output rate of 495 Mb/s for a single decoder. The corresponding ASIC implementation results in a 0.07 mm² design with the maximum output rate of 2.47 Gb/s. In addition to the decoder implementation results, we discuss other hardware implementation issues for the writer system data path, including on-chip input/output buffering, error propagation control, and input data stream packaging. This hardware data path implementation is independent of the writer systems or data link types, and can be integrated with arbitrary directwrite lithography systems.

Citation Download Citation

Hsin-I Liu, Brian Richards, Avideh Zakhor, and Borivoje Nikolic "Hardware implementation of Block GC3 lossless compression algorithm for direct-write lithography systems", Proc. SPIE 7637, Alternative Lithographic Technologies II, 763716 (2 April 2010); https://doi.org/10.1117/12.846447

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