This PDF file contains the front matter associated with SPIE Proceedings Volume 10321, including the Title Page, Copyright information, Table of Contents, and Conference Committee listing.

Until recently, lithography capability evolved consistently with Moore's law. It appears that semiconductor manufacturers are now deviating from Moore's law, which has implications for lithography equipment. DUV lithography is moving into production in a mix-and-match environment. Step- and-scan technology is the wave of the near- future, as a way to contend with the difficulty of manufacturing wide-field lenses. Resist processing equipment will undergo few fundamental changes, but will often be integrated with steppers, particularly for DUV applications. Metrology is being stretched beyond its limits for technologies below 250 nm. The move is on to 300 =I diameter wafers, and 193 nm lithography is under consideration.

It's has been the general opinion of device manufacturers that deep ultraviolet imaging will be the imaging method required to produce 250nm and sub-250nm geometry's for 256Mb-DRAM's and related logic technology. Traditional Mine lithography may not capable of manufacturing at these geometry's and the use of deep UV radiation with "chemically amplified" photoresists will be required for these device programs. Issues regarding the problems that researchers are combating or have not yet considered in the evolutionary chain of deep ultraviolet photoresist development and implementation will be discussed. As researchers continue developing environmentally stable materials, there is a series of issues that device manufacturers need to resolve today as new quarter micron fabs are currently under construction. Fab designers may need to consider additional space for specialty tools or processes in order to produce quarter micron lithography. The issues concerning materials, process, reflectivity control, manufacturing facilities, quality control, photoresist manufacturing, photoresist cost and a proposed roadmap for the next several years of development will be discussed. The author will also provide a brief overview of current Mine photoresists and their capability to the 300nm geometry region along with some basic chemistry regarding the principles of DNQ's and chemically amplified photoresists.

Metrology is the science of measurement. It is necessary for the development of new processes, the control and monitoring of existing ones, and as a product qualification yardstick. Microscopes are widely used to make precise distance measurements. They are especially important in the semiconductor industry where critical dimensions (CDs) are rapidly approaching 0.1 pm. The requirement in integrated circuit metrology that the fabrication tolerance be 10% of the critical dimension translates to a demanded measurement precision (between 10 - 40 % of the fabrication tolerance) on the single nanometer level. For example, the fabrication tolerance for a 0.25 pm nominal gate length would be 0.025 pm and the metrology precision around 0.0025 pm, or 2.5 nm - about five atoms long ! Similar arguments can be made for the relative (overlay) and absolute (placement) position of the feature as well. These metrology requirements were based upon a 10% rule and a new criterion or modification of this rule may have to be applied to the metrology requirements as the dimensions to be measured approach the nanometer scale. Submicrometer device fabrication metrology also involves performing measurements in three dimensions. Masks and wafers contain features with high aspect ratios and are composed of multiple layers of different materials; both factors make the theory and understanding of the metrology tool behavior complicated. In addition to measuring submicrometer feature dimensions and placements with nanometer-scale precision, high throughput and full automation are also desirable for an in-line manufacturing implementation. In this chapter, we will mainly be concerned with dimensional metrology of lithographic masks and patterned semiconductor wafer features after processing (post-fabrication); in particular, the measurement of feature width, height (depth), overlay, and placement. Because the theoretical limits of measurement capability are being approached, it is reasonable to believe that a shift in metrology from post fabrication sampling to on-line (in-situ) measurement and control is required to achieve more value in the metrology process. This change would require metrology instruments as robust as the processing equipment used in fabrication.

Introduction-Lithography is the key enabler for semiconductor manufacturing. Future progress in circuit scaling depends on continued progress in lithography capability scaling. Lithography is once again approaching a "barrier" where existing technology does not demonstrate a clear path for continued progress. We will explore some continuities and discontinuities in lithography that promise to drive the scaling process for many years

This presentation will review the key aspects of advanced photomask manufacturing and highlight the major technical challenges facing the mask industry. The bulk of the discussion will focus on mask technology for optical (248nm - 193nm wavelength) lithography, seen industry wide as the front up approach for 250nm to 180nm wafer dimension processing. After briefly establishing the business environment in which advanced optical mask development is done, current and future mask specifications are presented, the basic chrome on glass mask process is reviewed, and the major technical challenges facing each process segment are discussed in the context of high resolution lithography requirements. The basic principles involved in the two most mask intensive resolution enhancement techniques, optical proximity correction and phase shifted masks (alternating as well as attenuated) are reviewed and their specific technology challenges presented. A brief discussion of mask challenges in proximity x-ray lithography, the only viable near in alternative to optical lithography for this resolution range, will close out this presentation. The material is targeted at the general VLSI manufacturing and development community, it is not intended as a training course for mask development engineers.