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Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention [1]–[6]. Double patterning techniques in EUVL achieve pitch halving in the final feature by using the spacer defined approach and self-aligned block (SAB) mitigates the block placement error by leveraging etch selectivities and material filling capability. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER) [5]. In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects which can lead to device degradation by defect formation and edge-placement-error (EPE) [7]–[10]. LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our research, we examine three approaches to reduce LER on the EUV SADP line pattern. This includes photoresist surface smoothing techniques, patterning layer material study, and tone inversion integration. The photoresist surface smoothing techniques involve a specific plasma process on the EUV chemical amplified resist (CAR) to achieve > 15% of improvement on LER from lithography to post etch performance. The patterning layer material study reveals an optimum patterning stack to minimize etch-induced line wiggling and etch selectivity requirements for LER performance. Finally, a first demonstration of EUV SADP tone inversion process integration is presented as a method to provide additional benefits to LER reduction. A detailed analysis of line performance from each processing step will be examined.
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