Semiconductor device metrology for detecting defective chip due to high aspect ratio-based structures using hyperspectral imaging and deep learning

Sunhong Jun; Wonjun Choi; DongHoon Kim; Hayan Park; Dongmin Kyeon; Kyounghwan Lee; Yong-Ju Jeon; Chaemin Lee; Kwangchul Kim; Jeongsu Ha; Sungyoon Ryu; Younghoon Son; Yongdeok Jung

doi:10.1117/12.2657062

27 April 2023 Semiconductor device metrology for detecting defective chip due to high aspect ratio-based structures using hyperspectral imaging and deep learning

Sunhong Jun, Wonjun Choi, DongHoon Kim, Hayan Park, Dongmin Kyeon, Kyounghwan Lee, Yong-Ju Jeon, Chaemin Lee, Kwangchul Kim, Jeongsu Ha, Sungyoon Ryu, Younghoon Son, Yongdeok Jung

Author Affiliations +

Proceedings Volume 12496, Metrology, Inspection, and Process Control XXXVII; 124961F (2023) https://doi.org/10.1117/12.2657062
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Abstract

We developed imaging spectroscopic reflectometry (ISR) based on hyperspectral imaging and deep learning and built it as an in-line facility. After obtaining the reflectance as a hyperspectral cube of the 350 – 1100 nm wavelength region throughout the whole device wafer, dimension of the nanometer-sized structure can be imaged through the supervised learning model. In particular, by including near-IR region in the spectrum, the bottom critical dimension (BCD) of the high-aspect ratio structure such as channel hole (CHH) of the 3D NAND evaluated in this study can be imaged non-destructively and rapidly. After removing the top through decapsulation, the actual BCD was measured by SEM and was linked to the hyperspectral cube to construct a supervised learning model. The BCD predicted through ISR showed a correlation of R²=0.72 with the actual BCD. In addition, the shape of the defect on device chip caused by insufficient etch at the bottom of CHH, obtained by ISR was identical to the inspection image taken after decapsulation. Compared to spot measurement, ISR shows the advantage of being able to capture defects that occur at random locations in the device wafer. From our high volume sample of 3D NAND, ISR result showed a high correlation (R² = 0.82) with the rate of failure caused by channel hole while the conventional spot measurement showed only R² = 0.41. By using ISR, we could optimize the etching process for the wafer edge area where CHH formation is particularly weak.

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Sunhong Jun, Wonjun Choi, DongHoon Kim, Hayan Park, Dongmin Kyeon, Kyounghwan Lee, Yong-Ju Jeon, Chaemin Lee, Kwangchul Kim, Jeongsu Ha, Sungyoon Ryu, Younghoon Son, and Yongdeok Jung "Semiconductor device metrology for detecting defective chip due to high aspect ratio-based structures using hyperspectral imaging and deep learning", Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124961F (27 April 2023); https://doi.org/10.1117/12.2657062

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