Paper
10 August 2023 Improved Mersenne Twister random number generator based on FPGA
Weipu Liu, Jian Zhong, Sha Huan, Heng Li, Yuanjia Yang
Author Affiliations +
Proceedings Volume 12748, 5th International Conference on Information Science, Electrical, and Automation Engineering (ISEAE 2023); 127483P (2023) https://doi.org/10.1117/12.2689922
Event: 5th International Conference on Information Science, Electrical and Automation Engineering (ISEAE 2023), 2023, Wuhan, China
Abstract
With the development of the field of scientific computing, the rapid generation of high-quality random numbers has become a crucial aspect of research. However, traditional methods are often insufficient in meeting the efficiency and quality requirements of random number generation. In this paper, we propose an improved version of the Mersenne Twister algorithm, implemented on the FPGA platform. By optimizing the characteristic polynomial in the Transform module, the randomness and uniformity of the Mersenne Twister (MT) algorithm are enhanced. The core modules of the algorithm are realized through a parallel structure one the FPGA, with the AXI4-Stream data bus utilized as the protocol for data interaction with peripherals. Finally, the quality of the random numbers by the designed generator is tested, and the results demonstrate that it can efficiently produce high-quality, uniformly distributed random numbers. These numbers are well-suited for applications that require the rapid generation of large quantities and high-quality random numbers, such as Monte Carlo simulations.
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Weipu Liu, Jian Zhong, Sha Huan, Heng Li, and Yuanjia Yang "Improved Mersenne Twister random number generator based on FPGA", Proc. SPIE 12748, 5th International Conference on Information Science, Electrical, and Automation Engineering (ISEAE 2023), 127483P (10 August 2023); https://doi.org/10.1117/12.2689922
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KEYWORDS
Field programmable gate arrays

Power consumption

Computer simulations

Logic

Correlation coefficients

Mathematical optimization

Design and modelling

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