Hardware accelerator for linguistic data processing

Marian S. Stachowicz; Janos Grantner; Larry L. Kinney

doi:10.1117/12.57080

1 February 1992 Hardware accelerator for linguistic data processing

Marian S. Stachowicz, Janos Grantner, Larry L. Kinney

Proceedings Volume 1607, Intelligent Robots and Computer Vision X: Algorithms and Techniques; (1992) https://doi.org/10.1117/12.57080
Event: Robotics '91, 1991, Boston, MA, United States

Abstract

A hardware accelerator that performs fuzzy learning, fuzzy inference, and defuzzification strategy computations is presented in this paper. The hardware is based on two-valued logic. A universal space of 25 elements with five levels each is supported. To achieve a high processing rate for real-time applications, the basic units of the accelerator are connected in a four-level pipeline. The accelerator can receive two parallel fuzzy data as inputs. At a clock rate of 20 MHz, the accelerator can perform 800,000 fuzzy logic inferences per second on multidimensional fuzzy data.

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Marian S. Stachowicz, Janos Grantner, and Larry L. Kinney "Hardware accelerator for linguistic data processing", Proc. SPIE 1607, Intelligent Robots and Computer Vision X: Algorithms and Techniques, (1 February 1992); https://doi.org/10.1117/12.57080

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