New process for nanometer-scale devices

Yifang Chen; P. Hadley; C. J. P. M. Harmans; J. E. Mooij; Geok Ing Ng; Soon Fatt Yoon

doi:10.1117/12.280534

14 August 1997 New process for nanometer-scale devices

Yifang Chen, P. Hadley, C. J. P. M. Harmans, J. E. Mooij, Geok Ing Ng, Soon Fatt Yoon

Proceedings Volume 3183, Microlithographic Techniques in IC Fabrication; (1997) https://doi.org/10.1117/12.280534
Event: ISMA '97 International Symposium on Microelectronics and Assembly, 1997, Singapore, Singapore

Abstract

A new process employing e-beam lithography and a self- aligned tow angle shadow evaporation has been developed to fabricate 10 nm tunnel junctions and split leads with gaps of 2-5 nm. The fabricated Al/Al_xO/Al tunnel junctions on a SiO₂/Si substrate had a capacitance of 20 aF. These tunnel junctions were incorporated in single electron tunneling circuits where the small capacitance is essential. Single electron tunneling transistors with threshold voltages of 3 mV were fabricated using this process. The object of closely spaced leads was to contact individual molecules for electrical characterizations. Further improvements of this process for a triple angle shadow evaporation will be discussed.

Citation Download Citation

Yifang Chen, P. Hadley, C. J. P. M. Harmans, J. E. Mooij, Geok Ing Ng, and Soon Fatt Yoon "New process for nanometer-scale devices", Proc. SPIE 3183, Microlithographic Techniques in IC Fabrication, (14 August 1997); https://doi.org/10.1117/12.280534

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