Optimal implementation approach for discrete wavelet transform using FIR filter banks on FPGAs

Joe J. Sargunaraj; Sathyanarayana S. Rao

doi:10.1117/12.325722

2 October 1998 Optimal implementation approach for discrete wavelet transform using FIR filter banks on FPGAs

Joe J. Sargunaraj, Sathyanarayana S. Rao

Proceedings Volume 3461, Advanced Signal Processing Algorithms, Architectures, and Implementations VIII; (1998) https://doi.org/10.1117/12.325722
Event: SPIE's International Symposium on Optical Science, Engineering, and Instrumentation, 1998, San Diego, CA, United States

Abstract

We present a wavelet transform implementation approach using a FIR filter bank that uses a Wallace Tree structure for fast multiplication. VHDL models targeted specifically for synthesize have been written for clocked data registers, adders and the multiplier. Symmetric wavelets like Biorthogonal wavelets can be implemented using this design. By changing the input filter coefficients different wavelet decompositions may be implemented. The design is mapped onto the ORCA series FPGA after synthesis and optimization for timing and area.

Citation Download Citation

Joe J. Sargunaraj and Sathyanarayana S. Rao "Optimal implementation approach for discrete wavelet transform using FIR filter banks on FPGAs", Proc. SPIE 3461, Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, (2 October 1998); https://doi.org/10.1117/12.325722

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