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Highly interconnected multiprocessor systems are now performance limited by the backplane interconnection bottleneck associated with planar interconnection technologies. Smart pixel throughput capabilities are projected to exceed I Thitls/cm2 [1] and offer the promise of overcoming the bottlenecks of planar technologies for many types of interconnection-limited multiprocessor problems. Systems that use smart pixel-based free space optical interconnects (FSOI) provide two general dense interconnection capabilities: intelligent parallel data transfer and intelligent parallel data interchange. Optical imaging provides a high throughput approach to linking smart pixel planes for data transfer. In this case the high 110 density of smart pixels may provide a power consumption and size advantage over electronics [2,3]. For data interchange, FSOI provides the additional ability to perform the data partitioning and interleaving useful in space variant link interconnection patterns like the perfect shuffle (PS) [41,which are inherently difficult to implement in planar interconnection technologies. Such patterns are characterized by high BSBW [51. In multi-processor architecture design, there is a direct trade-off between minimum BSBW and latency in a network. It is therefore generally desirable to implement networks with the largest minimum BSBW that can be practically achieved to solve a given problem. The ability of optical elements to interconnect large arrays in space-variant patterns, without crosstalk in the medium, suggests that FSOI techniques are particularly promising for problems with high BSBW. For problems with greater than 1 ThitJsec BSBW (i.e., greater than the capabilities of a single chip) free space optical interconnects have a marked advantage [6,71. Therefore, globally interconnected multi-chip smart pixel based architectures have the potential to reap the full benefits of FSOI. This paper describes the experimental demonstration of a smart pixel based optical interconnection prototype currently being developed under the Free-space Accelerator for Switching Terabit tworks (FAST-Net) project, sponsored by the U.S. Defense Advanced Research Projects Agency. The prototype system incorporates 2-D arrays of monolithically integrated high-bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs). A key aspect of the FAST-Net concept is that all smart pixels are distributed across a single multi-chip plane. This plane is connected to itself via an optical system that consists of an array of matched lenses (one for each smart pixel chip position) and a mirror. The optical interconnect system implements a global point-to-point shuffle pattern. The interleaved 2-D arrays of VCSELs and PDs in the prototype are arranged on a clustered self-similar grid pattern with a closest element pitch of 100 tm. The circular VCSEL elements have a diameter of 10 pm and the square PDs have an active region that is 50 jim wide. These arrays are packaged and mounted on printed circuit boards along with CMOS driver, receiver, and FPGA controller chips. Micro-positioning mounts are used to effect alignment that is consistent with current MCM chip placement accuracy. Shuffled optical data links between the multiple ICs have been demonstrated in preliminary evaluation of this system. These results suggest that a multi-Terabit optically interconnected MCM module is feasible.
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