Sub-100-nm and deep sub-100-nm MOS transistor gate patterning

Qi Xiang; Subash Gupta; Chris A. Spence; Bhanwar Singh; Geoffrey C. Yeap; Ming-Ren Lin

doi:10.1117/12.323977

4 September 1998 Sub-100-nm and deep sub-100-nm MOS transistor gate patterning

Qi Xiang, Subash Gupta, Chris A. Spence, Bhanwar Singh, Geoffrey C. Yeap, Ming-Ren Lin

Proceedings Volume 3506, Microelectronic Device Technology II; (1998) https://doi.org/10.1117/12.323977
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

This paper reports experimental results of polysilicon gate patterning for sub-100 nm and deep sub-100 nm (less than 50 nm) MOS technology development. Sub-100 nm and deep sub-100 nm polysilicon gates have been achieved using an aggressive etch bias process combined with deep ultraviolet (DUV) lithography. In this paper, we report results on BARC effect, uniformity and iso/dense bias, etch selectivity, poly profile sensitivity, endcap pullback and metrology issues. We have achieved pitting free etch for ultra thin gate oxides down to 15 A. Deep sub-100 nm (approximately 50 nm) photo resist lines and deep sub-100 nm (less than 50 nm) poly gates with a good profile have been obtained.

Citation Download Citation

Qi Xiang, Subash Gupta, Chris A. Spence, Bhanwar Singh, Geoffrey C. Yeap, and Ming-Ren Lin "Sub-100-nm and deep sub-100-nm MOS transistor gate patterning", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323977

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