Ultrahigh-performance image processing architectures for hardware-in-the-loop testing

Allan J. Cantle; Malachy Devlin; Eric Lord

doi:10.1117/12.352893

19 July 1999 Ultrahigh-performance image processing architectures for hardware-in-the-loop testing

Allan J. Cantle, Malachy Devlin, Eric Lord

Proceedings Volume 3697, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing IV; (1999) https://doi.org/10.1117/12.352893
Event: AeroSense '99, 1999, Orlando, FL, United States

Abstract

Synthetic scene generation systems require huge computational resources to operate on potentially large data sets of information and to interface to advanced sensor technology via current scene projectors. Nallatech Ltd has been focused in the area of low latency hardware and algorithm development for many years. In collaboration with Matra British Aerospace Dynamics UK, minimum latency systems have already been developed offering latency of only several video lines in 3D target scene generation systems. The rapid progression of FPGAs towards 1 million gate devices together with the ever increasing performance of today's DSPs have allowed Nallatech to formulate an architecture that is particularly suited to HWIL systems.

Citation Download Citation

Allan J. Cantle, Malachy Devlin, and Eric Lord "Ultrahigh-performance image processing architectures for hardware-in-the-loop testing", Proc. SPIE 3697, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing IV, (19 July 1999); https://doi.org/10.1117/12.352893

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