10-Gb/s 1:4 demultiplexer in 0.25-um CMOS

Lei Tian; Zhigong Wang; Haitao Chen; Tingting Xie; Jianhua Lu; Rui Tao; Yi Dong; Shizhong Xie

doi:10.1117/12.444544

16 October 2001 10-Gb/s 1:4 demultiplexer in 0.25-μm CMOS

Lei Tian, Zhigong Wang, Haitao Chen, Tingting Xie, Jianhua Lu, Rui Tao, Yi Dong, Shizhong Xie

Proceedings Volume 4603, Fiber Optics and Optoelectronics for Network Applications; (2001) https://doi.org/10.1117/12.444544
Event: International Symposium on Optoelectonics and Microelectronics, 2001, Nanjing, China

Abstract

This paper described a 1:4 demultiplexer in a standard 0.25 micrometers CMOS. A tree-type structure is used to reduce the clock frequency and the SCL (Source Couple Logic) is used to construct high speed DFF. The chip occupies 1mm² area. It consumes 683mW from a 3.3 V supply. The operating bit rates is higher than 10Gb/s.

Citation Download Citation

Lei Tian, Zhigong Wang, Haitao Chen, Tingting Xie, Jianhua Lu, Rui Tao, Yi Dong, and Shizhong Xie "10-Gb/s 1:4 demultiplexer in 0.25-μm CMOS", Proc. SPIE 4603, Fiber Optics and Optoelectronics for Network Applications, (16 October 2001); https://doi.org/10.1117/12.444544

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