Employing Step and Flash imprint lithography for gate-level patterning of a MOSFET device

Britain J. Smith; Nicholas A. Stacey; J. P. Donnelly; David M. Onsongo; Todd C. Bailey; Chris J. Mackay; Douglas J. Resnick; William J. Dauksher; David P. Mancini; Kevin J. Nordquist; S. V. Sreenivasan; Sanjay K. Banerjee; John G. Ekerdt; Grant C. Willson

doi:10.1117/12.490142

16 June 2003 Employing Step-and-Flash imprint lithography for gate-level patterning of a MOSFET device

Britain J. Smith, Nicholas A. Stacey, J. P. Donnelly, David M. Onsongo, Todd C. Bailey, Chris J. Mackay, Douglas J. Resnick, William J. Dauksher, David P. Mancini, Kevin J. Nordquist, S. V. Sreenivasan, Sanjay K. Banerjee, John G. Ekerdt, Grant C. Willson

Author Affiliations +

Proceedings Volume 5037, Emerging Lithographic Technologies VII; (2003) https://doi.org/10.1117/12.490142
Event: Microlithography 2003, 2003, Santa Clara, California, United States

Abstract

Step and Flash Imprint Lithography (SFIL) is an alternative lithography technique that enables patterning of sub-100 nm features at a cost that has the potential to be substantially lower than either conventional projection lithography or proposed next generation lithography techniques. SFIL is a molding process that transfers the topography of a rigid transparent template using a low-viscosity, UV-curable organosilicon solution at room temperature and with minimal applied pressure. Employing SFIL technology we have successfully patterned areas of high and low density, semi-dense and isolated lines down to 20 nm, and demonstrated the capability of layer-to-layer alignment. We have also confirmed the use of SFIL to produce functional optical devices including a micropolarizer array consisting of orthogonal 100 nm titanium lines and spaces fabricated using a metal lift-off process. This paper presents a demonstration of the SFIL technique for the patterning of the gate level in a functional MOSFET device.

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Britain J. Smith, Nicholas A. Stacey, J. P. Donnelly, David M. Onsongo, Todd C. Bailey, Chris J. Mackay, Douglas J. Resnick, William J. Dauksher, David P. Mancini, Kevin J. Nordquist, S. V. Sreenivasan, Sanjay K. Banerjee, John G. Ekerdt, and Grant C. Willson "Employing Step-and-Flash imprint lithography for gate-level patterning of a MOSFET device", Proc. SPIE 5037, Emerging Lithographic Technologies VII, (16 June 2003); https://doi.org/10.1117/12.490142

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