Paper
10 July 2003 Characterization and modeling of intradie variation and its applications to design for manufacturability
Sharad Saxena, Carlo Guardiani, Michele Quarantelli, Nicola Dragone, Sean Minehane, Patrick McNamara, Jeff A. Babcock
Author Affiliations +
Abstract
Device scaling increases the impact of within-die variation or mismatch on the performance and yield of many important components of System on Chip (SoC) designs. This has created a need for accurate characterization, modeling, and simulation of mismatch. This paper provides a brief overview of the recent progress in these areas along with an example illustrating the application of these techniques to Design for Manufacturability (DFM) of Ultra Deep Submicron (UDSM) technologies.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sharad Saxena, Carlo Guardiani, Michele Quarantelli, Nicola Dragone, Sean Minehane, Patrick McNamara, and Jeff A. Babcock "Characterization and modeling of intradie variation and its applications to design for manufacturability", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); https://doi.org/10.1117/12.497477
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KEYWORDS
Design for manufacturability

Field effect transistors

System on a chip

Transistors

Instrument modeling

Manufacturing

Process control

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