A 64 x 64 CMOS digital pixel array based on pulse-width analog-to-digital conversion with on-chip linearizing circuit

Alistair J. Kitchen; Amine Bermak; Abdesselam Bouzerdoum

doi:10.1117/12.525558

30 March 2004 A 64 x 64 CMOS digital pixel array based on pulse-width analog-to-digital conversion with on-chip linearizing circuit

Alistair J. Kitchen, Amine Bermak, Abdesselam Bouzerdoum

Author Affiliations +

Proceedings Volume 5274, Microelectronics: Design, Technology, and Packaging; (2004) https://doi.org/10.1117/12.525558
Event: Microelectronics, MEMS, and Nanotechnology, 2003, Perth, Australia

Abstract

This paper describes a 64 x 64 digital pixel array employing a pulse width analogue to digital conversion scheme. Each pixel contains a photodiode sensor, comparator and memory, and in conjuction with a central control circuit performs the analogue to digital conversion, by timing a pulse generated by the photodiode/comparator circuit. The control circuit produces data which compensates for this nonlinear relationship, resulting in a pixel parallel ADC operation. The digital image data can be read from the array non-destructively, with random access. The array is constructed in a standard 0.35 μm, 3.3 V digital CMOS process.

Citation Download Citation

Alistair J. Kitchen, Amine Bermak, and Abdesselam Bouzerdoum "A 64 x 64 CMOS digital pixel array based on pulse-width analog-to-digital conversion with on-chip linearizing circuit", Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); https://doi.org/10.1117/12.525558

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