Speed-optimized ASIC turbo decoder core design

XiaoYi Chen; Qingdong Yao; Peng Liu

doi:10.1117/12.520206

28 April 2004 Speed-optimized ASIC turbo decoder core design

XiaoYi Chen, Qingdong Yao, Peng Liu

Proceedings Volume 5284, Wireless Communications and Networks; (2004) https://doi.org/10.1117/12.520206
Event: Asia-Pacific Optical and Wireless Communications, 2003, Wuhan, China

Abstract

Turbo codes are now universally known as one of the most effective techniques for achieving performance very close to the Shannon theoretical limits in many transmission systems. This paper presents a speed optimized ASIC turbo decoder core's design. The proposed architectures achieve a complexity reduction. Because of the recursion algorithm, the result of recursion is used immediately in following cycle. A reasonable pipeline is adopted by averaged the critical path to eliminate this effect. Core is fit to realize not only in FPGA, but also can embedded into other DSP and the decode rate can reach 6 Mbps in 0.18 um technology.

Citation Download Citation

XiaoYi Chen, Qingdong Yao, and Peng Liu "Speed-optimized ASIC turbo decoder core design", Proc. SPIE 5284, Wireless Communications and Networks, (28 April 2004); https://doi.org/10.1117/12.520206

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