Post-CMOS chip-level processing for high-aspect-ratio microprobe fabrication utilizing pulse plating

Tinghui Xin; Pratul K. Ajmera; Chuang Zhang; Ashok Srivastava

doi:10.1117/12.600128

16 May 2005 Post-CMOS chip-level processing for high-aspect-ratio microprobe fabrication utilizing pulse plating

Tinghui Xin, Pratul K. Ajmera, Chuang Zhang, Ashok Srivastava

Proceedings Volume 5763, Smart Structures and Materials 2005: Smart Electronics, MEMS, BioMEMS, and Nanotechnology; (2005) https://doi.org/10.1117/12.600128
Event: SPIE Smart Structures and Materials + Nondestructive Evaluation and Health Monitoring, 2005, San Diego, California, United States

Abstract

A post-CMOS process for chip-level monolithic integration has been developed. A metal probe array for recording neural signals is utilized as a test vehicle to realize the integration process. This probe array is fabricated on a 2 mm x 2 mm chip containing eight ultra-low power CMOS operational amplifiers. A LIGA-like process is employed utilizing UV lithography on SU-8 photoresist and pulse electroplating technique. Pulse plating significantly reduces stress in the deposited material. The post-CMOS fabrication process is utilized to fabricate 70 μm high probes having different aspect-ratios that are monolithically integrated on the CMOS chip.

Citation Download Citation

Tinghui Xin, Pratul K. Ajmera, Chuang Zhang, and Ashok Srivastava "Post-CMOS chip-level processing for high-aspect-ratio microprobe fabrication utilizing pulse plating", Proc. SPIE 5763, Smart Structures and Materials 2005: Smart Electronics, MEMS, BioMEMS, and Nanotechnology, (16 May 2005); https://doi.org/10.1117/12.600128

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