Optical lithography applied to 20-nm CMOS Logic and SRAM

V. Axelrad; M. C. Smayling; K. Tsujita; K. Takahashi

doi:10.1117/12.879522

22 March 2011 Optical lithography applied to 20-nm CMOS Logic and SRAM

V. Axelrad, M. C. Smayling, K. Tsujita, K. Takahashi

Proceedings Volume 7973, Optical Microlithography XXIV; 797314 (2011) https://doi.org/10.1117/12.879522
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

Achieving 20nm designs with 193nm lithography is difficult even with immersion technology. At 20nm, the metal-1 pitch will be ~64nm, which is well below the 80nm limit for single exposure. In this work we extend on our earlier results [1-4] to show simulation-based patterning of both SRAMs and logic cells. This is consistent with the emerging industry consensus that regular designs and multiple exposure techniques will extend 193nm immersion as far down as 7nm [5]. The approach relies on 1D Gridded Design Rules with Lines/Cuts (1D GDR LC) selective double patterning. Due to the highly regular patterns of 1D GDR LC we are able to determine a sharp lithographic optimum as a result of numerical co-optimization of key layout parameters and lithography settings such as scanner illumination, etc. including realistic scanner capability. Critical layers (holes/cuts in 1D GDR LC) consist of a number of identical hole/cut patterns with varying density. We propose a novel algorithm for full-chip proximity correction of such critical layers. The algorithm consists of 1) a source-mask optimization step (SMO) to choose optimal scanner settings for a class of designs using standard cells, followed by 2) a final correction step applied to the entire layout to determine individual sizing for each cut to componsate for its optical/process environment. This procedure converges rapidly in our test cases producing close to 0nm CD error for each cut. Several test designs including one with approximately 100k transistors using ~20 cells from a standard cell library including both SRAM and logic cells were used, with good convergence obtained in all cases. Out procedure is a combination of an SMO step followed by cuts-OPC, the equivalent to OPC applied to cuts of 1D GDR LC designs. The procedure scales linearly with layout area and can be efficiently applied to full-chip designs.

Citation Download Citation

V. Axelrad, M. C. Smayling, K. Tsujita, and K. Takahashi "Optical lithography applied to 20-nm CMOS Logic and SRAM", Proc. SPIE 7973, Optical Microlithography XXIV, 797314 (22 March 2011); https://doi.org/10.1117/12.879522

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