High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology

Jieming Ma; Ka Lok Man; Nan Zhang; Sheng-Uei Guan; Taikyeong Ted. Jeong

doi:10.1117/12.2014353

13 March 2013 High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology

Jieming Ma, Ka Lok Man, Nan Zhang, Sheng-Uei Guan, Taikyeong Ted. Jeong

Author Affiliations +

Proceedings Volume 8784, Fifth International Conference on Machine Vision (ICMV 2012): Algorithms, Pattern Recognition, and Basic Technologies; 87841Z (2013) https://doi.org/10.1117/12.2014353
Event: Fifth International Conference on Machine Vision (ICMV 12), 2012, Wuhan, China

Abstract

Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and power-aware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.

Citation Download Citation

Jieming Ma, Ka Lok Man, Nan Zhang, Sheng-Uei Guan, and Taikyeong Ted. Jeong "High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology", Proc. SPIE 8784, Fifth International Conference on Machine Vision (ICMV 2012): Algorithms, Pattern Recognition, and Basic Technologies, 87841Z (13 March 2013); https://doi.org/10.1117/12.2014353

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