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An integrated photonic circuit architecture to perform a modified-convolution operation based on the discrete fractional Fourier transform (DFrFT) is introduced. This is accomplished by utilizing two nonuniformly-coupled waveguide lattices of different lengths that perform DFrDT operations of complementary orders. Numerical simulations show that smoothing and edge detection tasks are indeed performed even for noisy input signals. A design recipe based on the standard silicon-on-insulator fabrication technology is provided. The scaling properties of the proposed architecture are discussed. Finally, the use of the proposed photonic convolutional accelerator for chip-scale photonic AI systems is discussed.
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