This PDF file contains the editorial “Our Top Reviewers of 2015” for JM3 Vol. 15 Issue 01

This PDF file contains the editorial “2015 List of Reviewers” for JM3 Vol. 15 Issue 01

Solid-state technology has enabled the use of light-emitting diodes (LEDs) in lithography systems due to their low cost, low power requirement, and higher efficiency relative to the traditional mercury lamp. Uniform irradiance distribution is essential for photolithography to ensure the critical dimension (CD) of the feature fabricated. However, light illuminated from arrays of LEDs can have nonuniform irradiance distribution, which can be a problem when using LED arrays as a source to batch-fabricate multiple devices on a large wafer piece. In this study, the irradiance distribution of an UV LED array was analyzed, and the separation distance between light source and mask optimized to obtain maximum irradiance uniformity without the use of a complex lens. Further, employing a diffuser glass enhanced the fabrication process and the CD loss was minimized to an average of 300 nm. To assess the performance of the proposed technology, batch fabrication of surface acoustic wave devices on lithium niobate substrate was carried out, and all the devices exhibited identical insertion loss of −18  dB at a resonance frequency of 39.33 MHz. The proposed low-cost UV lithography setup can be adapted in academic laboratories for research and teaching on microdevices.

We described the effect of the ultraviolet ozone (UVO) treatment of a polydimethylsiloxane (PDMS) stamp on the fidelity of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PEN) patterns produced from a TIPS-PEN/polymer blend by selective contact evaporation (SCE). During the SCE process, the TIPS-PEN in contact with the nanoporous PDMS was absorbed into the PDMS stamp, leaving out the TIPS-PEN patterns, complementary to the PDMS patterns, in the noncontact regions. For the case of the untreated, hydrophobic PDMS surface, the TIPS-PEN patterns developed initially were shrunken and eventually disappeared after 24 h due to the steady absorption of the TIPS-PEN in time. In contrast, for the UVO-treated case, the TIPS-PEN patterns were found to maintain the initial shapes over the period of 24 h since the absorption of the TIPS-PEN was limited by the hydrophilic nature of the UVO-treated PDMS. The modified PDMS surface by the UVO for 30 min yielded the highest fidelity of the TIPS-PEN patterns in both height and width. The patterned TIPS-PEN layer by the SCE was implemented into an organic field-effect transistor to demonstrate the viability of the SCE combined with the UVO treatment for solution-processed organic electronic devices.

It is shown experimentally that the irradiation of thin Al and Au films of thickness 50 to 100 nm on a silicate glass surface by electrons results in effects that differ principally depending on the electron energy. For energies of 5 to 15 keV, the irradiation leads to an increase in the film thickness throughout the irradiated zone and a decrease in the thickness in the surrounding area. For an energy of 25 keV, the irradiation leads to dissolving the Au film in glass in the irradiated zone. The mechanisms of the observed effects are discussed.

A theoretical model for describing the propagation and scattering of energetic species in an extreme ultraviolet (EUV) light lithography source is presented. An EUV light emitting XTREME XTS 13-35 Z-pinch plasma source is modeled with a focus on the effect of chamber pressure and buffer gas mass on energetic ion and neutral debris transport. The interactions of the energetic debris species, which is generated by the EUV light emitting plasma, with the buffer gas and chamber walls are considered as scattering events in the model, and the trajectories of the individual atomic species involved are traced using a Monte Carlo algorithm. This study aims to establish the means by which debris is transported to the intermediate focus with the intent to verify the various mitigation techniques currently employed to increase EUV lithography efficiency. The modeling is compared with an experimental investigation.

Early identification of problematic patterns in very large scale integration (VLSI) designs is of great value as the lithographic simulation tools face significant timing challenges. To reduce the processing time, such a tool selects only a fraction of possible patterns which have a probable area of failure, with the risk of missing some problematic patterns. We introduce a fast method to automatically extract patterns based on their structure and context, using the Voronoi diagram of line-segments as derived from the edges of VLSI design shapes. Designers put line segments around the problematic locations in patterns called “gauges,” along which the critical distance is measured. The gauge center is the midpoint of a gauge. We first use the Voronoi diagram of VLSI shapes to identify possible problematic locations, represented as gauge centers. Then we use the derived locations to extract windows containing the problematic patterns from the design layout. The problematic locations are prioritized by the shape and proximity information of the design polygons. We perform experiments for pattern selection in a portion of a 22-nm random logic design layout. The design layout had 38,584 design polygons (consisting of 199,946 line segments) on layer Mx, and 7079 markers generated by an optical rule checker (ORC) tool. The optical rules specify requirements for printing circuits with minimum dimension. Markers are the locations of some optical rule violations in the layout. We verify our approach by comparing the coverage of our extracted patterns to the ORC-generated markers. We further derive a similarity measure between patterns and between layouts. The similarity measure helps to identify a set of representative gauges that reduces the number of patterns for analysis.

In a 7 nm node (N7), the logic design requires a critical poly pitch of 42 to 45 nm and a metal 1 (M1) pitch of 28 to 32 nm. Such high-pattern density pushes the 193 immersion lithography solution toward its limit and also brings extremely complex patterning scenarios. The N7 M1 layer may require a self-aligned quadruple patterning (SAQP) with a triple litho-etch (LE³) block process. Therefore, the whole patterning process flow requires multiple exposure+etch+deposition processes and each step introduces a particular impact on the pattern profiles and the topography. In this study, we have successfully integrated a simulation tool that enables emulation of the whole patterning flow with realistic process-dependent three-dimensional (3-D) profile and topology. We use this tool to study the patterning process variations of the N7 M1 layer including the overlay control, the critical dimension uniformity budget, and the lithographic process window (PW). The resulting 3-D pattern structure can be used to optimize the process flow, verify design rules, extract parasitics, and most importantly, simulate the electric field, and identify hot spots for dielectric reliability. As an example application, the maximum electric field at M1 tip-to-tip, which is one of the most critical patterning locations, has been simulated and extracted. The approach helps to investigate the impact of process variations on dielectric reliability. We have also assessed the alternative M1 patterning flow with a single exposure block using extreme ultraviolet lithography (EUVL) and analyzed its advantages compared to the LE³ block approach.

Source optimization is one of the key techniques for achieving higher resolution without increasing the complexity of mask design. An efficient source optimization approach is proposed on the basis of particle swarm optimization. The pixelated sources are encoded into particles, which are evaluated by using the pattern error as the fitness function. Afterward, the optimization is implemented by updating the velocities and positions of these particles. This approach is demonstrated using three mask patterns, including a periodic array of contact holes, a vertical line/space design, and a complicated pattern. The pattern errors are reduced by 69.6%, 51.5%, and 40.3%, respectively. Compared with the source optimization approach via genetic algorithm, the proposed approach leads to faster convergence while improving the image quality at the same time. Compared with the source optimization approach via gradient descent method, the proposed approach does not need the calculation of gradients, and it has a strong adaptation to various lithographic models, fitness functions, and resist models. The robustness of the proposed approach to initial sources is also verified.

Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed.

State-of-the-art block copolymer (BCP)—directed self-assembly (DSA) methods still yield defect densities orders of magnitude higher than is necessary in semiconductor fabrication despite free-energy calculations that suggest equilibrium defect densities are much lower than is necessary for economic fabrication. This disparity suggests that the main problem may lie in the kinetics of defect removal. This work uses a coarse-grained model to study the rates, pathways, and dependencies of healing a common defect to give insight into the fundamental processes that control defect healing and give guidance on optimal process conditions for BCP-DSA. It is found that bulk simulations yield an exponential drop in defect heal rate above χN∼30. Thin films show no change in rate associated with the energy barrier below χN∼50, significantly higher than the χN values found previously for self-consistent field theory studies that neglect fluctuations. Above χN∼50, the simulations show an increase in energy barrier scaling with 1/2 to 1/3 of the bulk systems. This is because thin films always begin healing at the free interface or the BCP-underlayer interface, where the increased A−B contact area associated with the transition state is minimized, while the infinitely thick films cannot begin healing at an interface.

Most approaches to model-based optical proximity correction (OPC) use an iterative algorithm to determine the optimum mask. Each iteration requires at least one simulation, which is the most time-consuming part of model-based OPC. As the layout becomes more complicated and the process conditions are driven to the physical limit, the required number of iterations increases dramatically. To overcome this problem, we propose a method to predict the OPC bias of layout segments with a single-hidden-layer neural network. The segments are characterized by length and based on intensities at the corresponding control points, and these features are used as input to the network, which is trained with an extreme learning machine. We obtain a best-error root mean square of 1.29 nm from training and test experiments for layout clips sampled from a random contact layer of a logic device. In addition, we reduced the iterations by 27.0% by initializing the biases in the trained network before performing the main iterations of the OPC algorithm.

Defect detectability using electron-beam (EB) inspection for an extreme ultraviolet (EUV) mask was investigated by comparing a projection electron microscope (PEM) and a scanning electron microscope (SEM) inspection system. The detectability with EB does not coincide with the printability data because the contrasts of the EUV aerial image and EB image for EUV mask are reversed. The 16-nm-sized defect on a half-pitch 64-nm line and space (L/S) pattern is detected even when the line edge roughness is taken into account in both PEM and SEM inspections by applying a special algorithm for image processing. The required and robust inspection conditions, such as the number of electrons per pixel and pixel size (resolution), were examined for an SEM inspection system. The throughput of the PEM inspection system corresponds to that of the multibeam SEM one with 200 to 1850 beams.

Grayscale lithography is a relatively underutilized technique that enables fabrication of three-dimensional (3-D) microstructures in photosensitive polymers (photoresists). By spatially modulating ultraviolet (UV) dosage during the writing process, one can vary the depth at which photoresist is developed. This means complex structures and bioinspired designs can readily be produced that would otherwise be cost prohibitive or too time intensive to fabricate. The main barrier to widespread grayscale implementation, however, stems from the laborious generation of mask files required to create complex surface topography. We present a process and associated software utility for automatically generating grayscale mask files from 3-D models created within industry-standard computer-aided design (CAD) suites. By shifting the microelectromechanical systems (MEMS) design onus to commonly used CAD programs ideal for complex surfacing, engineering professionals already familiar with traditional 3-D CAD software can readily utilize their pre-existing skills to make valuable contributions to the MEMS community. Our conversion process is demonstrated by prototyping several samples on a laser pattern generator—capital equipment already in use in many foundries. Finally, an empirical calibration technique is shown that compensates for nonlinear relationships between UV exposure intensity and photoresist development depth as well as a thermal reflow technique to help smooth microstructure surfaces.

A line grating prepared via a self-aligned quadruple patterning method was measured using critical dimension small angle x-ray scattering. A Monte Carlo Markov chain algorithm was used to analyze the uncertainty of the model fit over subsets of the full angular range and for a time series with decreasing signal-to-noise in order to determine the effect of the data quality on the final profile shape uncertainty. These results show how the total measurement time can be reduced while maintaining satisfactory profile shape uncertainty. We found that the typical measurement conditions are highly oversampled and can be reduced considerably with only marginal effect on the shape uncertainty. A comparison is made between the synchrotron measurements and a laboratory system, demonstrating that both measurements result in similar structures.

This paper proposes a method for the characterization of multilayer defects from extreme ultraviolet (EUV) projection images at different focus positions. The transport-of-intensity equation is applied to retrieve the phase distribution of the reflected light in the vicinity of the defect. The defect-induced intensity and phase modifications and their dependency from defect geometry parameters are analyzed by several selected optical properties of multilayer defect. To reconstruct the defect geometry parameters from the intensity and phase of a defect, a principal component analysis (PCA) is employed to parameterize the intensity and phase distributions into principal component coefficients. In order to construct the base functions of the PCA, a combination of a reference multilayer defect and appropriate pupil filters is introduced to obtain the designed sets of intensity and phase distributions. Finally, an artificial neural network is applied to correlate the principal component coefficients of the intensity and the phase of the defect with the defect geometry parameters and to reconstruct the unknown defect geometry parameters. The performance of the proposed approach is evaluated both for mask blank defects and for defects in the vicinity of an absorber pattern.

Sidewall sensing in critical dimension atomic force microscopes (CD-AFMs) usually involves continuous lateral dithering of the tip or the use of a control algorithm and fast response piezoactuator to position the tip in a manner that resembles touch-triggering of coordinate measuring machine probes. All methods of tip position control, however, induce an effective tip width that may deviate from the actual geometrical tip width. Understanding the influence and dependence of the effective tip width on the dither settings and lateral stiffness of the tip can improve the measurement accuracy and uncertainty estimation for CD-AFM measurements. Since CD-AFM typically uses tips that range from 15 to 850 nm in geometrical width, the behavior of effective tip width throughout this range should be understood. The National Institute of Standards and Technology (NIST) has been investigating the dependence of effective tip width on the dither settings and lateral stiffness of the tip, as well as the possibility of material effects due to sample composition. For tip widths of 130 nm and lower, which also have lower lateral stiffness, the response of the effective tip width to lateral dither is greater than for larger tips. However, we have concluded that these effects will not generally result in a residual bias, provided that the tip calibration and sample measurement are performed under the same conditions. To confirm that our prior conclusions about the dependence of effective tip width on lateral stiffness are valid for large CD tips, we recently performed experiments using a very large non-CD tip with an etched plateau of ∼2-μm width. The effective lateral stiffness of these tips is at least 20 times greater than typical CD-AFM tips, and these results supported our prior conclusions about the expected behavior for larger tips. The bottom-line importance of these latest observations is that we can now reasonably conclude that a dither slope of 3  nm/V is the baseline response due to the induced motion of the cantilever base.

Directed self-assembly (DSA) is a potential patterning solution for future generations of integrated circuits. Its main advantages are high pattern resolution (∼10  nm), high throughput, no requirement of high-resolution mask, and compatibility with standard fab-equipment and processes. The application of Mueller matrix (MM) spectroscopic ellipsometry-based scatterometry to optically characterize DSA patterned contact hole structures fabricated with phase-separated polystyrene-b-polymethylmethacrylate (PS-b-PMMA) is described. A regression-based approach is used to calculate the guide critical dimension (CD), DSA CD, height of the PS column, thicknesses of underlying layers, and contact edge roughness of the post PMMA etch DSA contact hole sample. Scanning electron microscopy and imaging analysis is conducted as a comparative metric for scatterometry. In addition, optical model-based simulations are used to investigate MM elements’ sensitivity to various DSA-based contact hole structures, predict sensitivity to dimensional changes, and its limits to characterize DSA-induced defects, such as hole placement inaccuracy, missing vias, and profile inaccuracy of the PMMA cylinder.

Nanogratings with different duty cycles are directly written on gold films using interference ablation. After exposing the gold film to the interference pattern of ultraviolet laser beams, gold film in the bright fringes will be melted and ablated, whereas much weaker ablation occurs in the dark fringes. The duty cycle of gold nanogratings can be controlled by adjusting the pulse energy and the exposure times, which can be explained by the temperature rise and cumulative effect of the laser–metal interactions. These results introduce additional parameters for the fine fabrication of metal nanogratings based on interference ablation at a large scale and low cost.

Pattern-integrated interference lithography (PIIL) combines multibeam interference lithography and projection lithography simultaneously to produce two-dimensional (2-D) and three-dimensional (3-D) periodic-lattice-based microstructures in a rapid, single-exposure step. Using a comprehensive PIIL vector model and realistic photolithographic conditions, PIIL exposures for a representative photonic-crystal (PhC) 90 deg bend waveguide are simulated in the volume of the photoresist film. The etched structures in the underlying substrate are estimated as well. Due to the imperfect integration of the photomask within the interference pattern, the interference pattern is locally distorted, thereby impacting the PhC periodic lattice and potentially the device performance. To mitigate these distortions, a photomask optimization method for PIIL is presented in this work. With an improved photomask, pillar-area and pillar-displacement errors in the vicinity of the waveguide are reduced by factors of 3.3 and 2.7, respectively. Furthermore, calculated transmission spectra show that the performance of the PIIL-produced PhC device is as good as that of its idealized equivalent.

Lattice-selective etching of silicon is used in a number of applications, but it is particularly valuable in those for which the lattice-defined sidewall angle can be beneficial to the functional goals. A relatively small but important niche application is the fabrication of tip characterization standards for critical dimension atomic force microscopes (CD-AFMs). CD-AFMs are commonly used as reference tools for linewidth metrology in semiconductor manufacturing. Accurate linewidth metrology using CD-AFM, however, is critically dependent upon calibration of the tip width. Two national metrology institutes and at least two commercial vendors have explored the development of tip calibration standards using lattice-selective etching of crystalline silicon. The National Institute of Standards and Technology standard of this type is called the single crystal critical dimension reference material. These specimens, which are fabricated using a lattice-plane-selective etch on (110) silicon, exhibit near vertical sidewalls and high uniformity and can be used to calibrate CD-AFM tip width to a standard uncertainty of less than 1 nm. During the different generations of this project, we evaluated variations of the starting material and process conditions. Some of our starting materials required a large etch bias to achieve the desired linewidths. During the optimization experiment described in this paper, we found that for potassium hydroxide etching of the silicon features, it was possible to independently tune the target linewidth and minimize the linewidth nonuniformity. Consequently, this process is particularly well suited for small-batch fabrication of CD-AFM linewidth standards.

A microaccelerometer based on gallium arsenide (GaAs) resonant-tunneling diodes (RTDs) is demonstrated. The input acceleration signal can be transformed into an output electrical signal using the meso-piezoresistive effects of the RTDs located at the root of the detection beams. Finite element simulations were performed to design, analyze, and optimize the structures of the accelerometer. The accelerometer was fabricated using a combination of GaAs IC surface and bulk micromachining techniques. Vibrating tests and shock tests were conducted to investigate the accelerometer characteristics. The experimental results revealed that the sensitivity of the RTD accelerometer was 7.91  mV/g. The noise resolution was ∼1.264  mg/√Hz, and the working frequency was up to 3 kHz.

To assess the charge-injection capacity of the sputtered iridium oxide film (SIROF) electrode on the retinal CMOS image sensor (CIS) chip, a polyimide-based flex device was designed and fabricated to package the retinal CIS chip. The polyimide-flex-based packaging process keeps the surface of photosensors clean, and the measured connection resistance meets the packaging requirement of the low-power retinal CIS chip. The in vitro experimental results show that the small SIROF electrodes can provide a biphasic charge injection per phase of 3.9  nC/ph to achieve the stimulation threshold at a polarization potential of −0.44  V.

This work proposes an architecture for a wide-angle, self-aligned, in-plane monolithic scanner fabricated using the deep reactive ion etching technology. The fabricated microscanner provides an optical scanning in-plane angle of about 86 deg and operates at the speed of 2.73 kHz. The scanning is achieved using two synchronized, flat mirrors coupled mechanically to allow for wide-angle scanning and connected through a compliant structure to allow the use of a linear comb actuator. This wide-angle, in-plane scanning opens the door for many applications, especially for handheld optical displays.