Antonios Gasteratos, Ioannis Andreadis, Phillippos Tsalides
Optical Engineering, Vol. 36, Issue 03, (March 1997) https://doi.org/10.1117/1.601140
TOPICS: Image processing, Very large scale integration, Image resolution, Mathematical morphology, Binary data, Signal processing, Optical engineering, Multiplexers, Detection and tracking algorithms, Silicon
This paper presents the design and VLSI implementation of a new ASIC that performs in real time the morphological operations of dilation and erosion. The ASIC’s architecture is based on the extension of the majority-gate algorithm for morphological operations. The ASIC was implemented using a DLM, 0.7-?m, CMOS, N-well process, and it occupies a silicon area of 14.78 mm2. Its maximum speed of operation is 92.5 MHz. Targeted applications include machine vision, where the need for short processing times is crucial.