The market transition from 2D to 3D-NAND in recent years requires strict focus control and monitoring solutions. ASML’s μDBF targets (micro Diffraction Based Focus) enable on-product focus measurement which can be used to optimize scanner correction. Additionally, dense computational focus maps can be generated by combining μDBF measurements with scanner metrology such as non-correctable leveling error. This paper discusses the focus variability observed on memory layers through on product focus monitoring. This work will show how exposure at best focus can be performed for immersion lithography in the case of strong focus fingerprints. Focus monitoring data from μDBF and computational focus metrology will be used to generate and apply corrections on two 3D-NAND layers.
The usage of convolutional neural networks (CNN) on images is spreading into various topics in lot of industries. Today in the semiconductor industry CNN are used to perform Automatic Defect Classification (ADC) on SEM review images in almost real time and with level of success as high as trained operators can do or more [1,2]. The possibilities to get new kind of information from images offer to engineers multiple potential usages. In this paper we propose to present derivatives usages of CNN applied to the CD-SEM metrology with specific focus on an application to detect undermelted microlens in our imager process flow [3]. CD-SEM metrology is used to perform Critical Dimension (CD) measurement on almost all patterning steps in the wafer cycle (after lithography and after etch). CNN allows us to get more information from pictures than only dimensions measured by the CD-SEM used to feed a control card. In our imager process flow we have steps to form microlenses. The microlens process fabrication consists in a first lithography step where microlens matrix is defined in resist. The result is a matrix of quite square parallelepipoid microlenses followed by a melting step in order to reflow resists and eventually form microlens with spherical cap shape. The figure 1 shows the evolution of microlens shape in function of melting process time.
From the first digital cameras which appeared during the 70s to cameras of current smartphones, image sensors have undergone significant technological development in the last decades. The development of CMOS image sensor technologies in the 90s has been the main driver of the recent progresses. The main component of an image sensor is the pixel. A pixel contains a photodiode connected to transistors but only the photodiode area is light sensitive. This results in a significant loss of efficiency. To solve this issue, microlenses are used to focus the incident light on the photodiode. A microlens array is made out of a transparent material and has a spherical cap shape. To obtain this spherical shape, a lithography process is performed to generate resist blocks which are then annealed above their glass transition temperature (reflow).
Even if the dimensions to consider are higher than in advanced IC nodes, microlenses are sensitive to process variability during lithography and reflow. A good control of the microlens dimensions is key to optimize the process and thus the performance of the final product.
The purpose of this paper is to apply SEM contour metrology [1, 2, 3, 4] to microlenses in order to develop a relevant monitoring methodology and to propose new metrics to engineers to evaluate their process or optimize the design of the microlens arrays.
Today’s technology nodes contain more and more complex designs bringing increasing challenges to chip manufacturing process steps. It is necessary to have an efficient metrology to assess process variability of these complex patterns and thus extract relevant data to generate process aware design rules and to improve OPC models. Today process variability is mostly addressed through the analysis of in-line monitoring features which are often designed to support robust measurements and as a consequence are not always very representative of critical design rules. CD-SEM is the main CD metrology technique used in chip manufacturing process but it is challenged when it comes to measure metrics like tip to tip, tip to line, areas or necking in high quantity and with robustness. CD-SEM images contain a lot of information that is not always used in metrology. Suppliers have provided tools that allow engineers to extract the SEM contours of their features and to convert them into a GDS. Contours can be seen as the signature of the shape as it contains all the dimensional data. Thus the methodology is to use the CD-SEM to take high quality images then generate SEM contours and create a data base out of them. Contours are used to feed an offline metrology tool that will process them to extract different metrics. It was shown in two previous papers that it is possible to perform complex measurements on hotspots at different process steps (lithography, etch, copper CMP) by using SEM contours with an in-house offline metrology tool. In the current paper, the methodology presented previously will be expanded to improve its robustness and combined with the use of phylogeny to classify the SEM images according to their geometrical proximities.
Today’s CD-SEM metrology is challenged when it comes to measuring complex features found in patterning hotspots (like tip to tip, tip to side, necking and bridging). Metrology analysis tools allow us to extract SEM contours of a feature and convert them into a GDS format from which dimensional data can be extracted. While the CD-SEM is being used to take images, the actual measurement and the choice of what needs to be measured is done offline. Most of the time this method is used for OPC model creation but barely for process variability analysis at nominal process conditions. We showed in a previous paper [1] that it is possible to study lithography to etch transfer behavior of a hotspot using SEM contours. The goal of the current paper is to go extend this methodology to quantify process variability of 2D features using a new tooling to measure contour data.
At 28nm technology node and below, hot spot prediction and process window control across production wafers have become increasingly critical to prevent hotspots from becoming yield-limiting defects. We previously established proof of concept for a systematic approach to identify the most critical pattern locations, i.e. hotspots, in a reticle layout by computational lithography and combining process window characteristics of these patterns with across-wafer process variation data to predict where hotspots may become yield impacting defects [1,2]. The current paper establishes the impact of micro-topography on a 28nm metal layer, and its correlation with hotspot best focus variations across a production chip layout. Detailed topography measurements are obtained from an offline tool, and pattern-dependent best focus (BF) shifts are determined from litho simulations that include mask-3D effects. We also establish hotspot metrology and defect verification by SEM image contour extraction and contour analysis. This enables detection of catastrophic defects as well as quantitative characterization of pattern variability, i.e. local and global CD uniformity, across a wafer to establish hotspot defect and variability maps. Finally, we combine defect prediction and verification capabilities for process monitoring by on-product, guided hotspot metrology, i.e. with sampling locations being determined from the defect prediction model and achieved prediction accuracy (capture rate) around 75%
In the early phases of technology development, designers and process engineers have to converge
toward efficient design rules. Their calculations are based on process assumptions and result in a
design rule based on known process variability capabilities while taking into account enough margin
to be safe not only for yield but especially for reliability. Unfortunately, even if designs tend to be
regular, efficient design densities are still requiring aggressive configurations from which it is
difficult to estimate dimension variabilities.
Indeed, for a process engineer it is rather straightforward to estimate or even measure simple one-dimensional
features (arrays of Lines & Spaces at various CD and pitches), but it starts to be less
obvious for complex multidimensional features. After a context description related to the process
assumptions, we will outline the work flow which is under evaluation to enable robust metrology of
2 dimensional complex features.
Enabling new metrology possibilities reveals that process hotspots are showing complex behavior
from lithography to etch pattern transfer.
In this work we studied the interaction of lithography variability and etching for a mature 28 nm
CMOS process. To study this interaction we used a test feature that has been found very sensitive to
lithography process variations. This so-called “golden” hotspot shows edge-to-edge geometries from
88nm to 150nm, thus comprising all the through pitch physics in the lithography pattern transfer [1,
2]. It consists of three trenches. From previous work it was known that through trench there is a
systematic variation in best focus due to the Mask 3D effects. At a given chosen focus, there is a
distinct difference in profiles for the three trenches that will lead to pattern displacement effects
during the etch transfer.
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