We have been developing an ultra high definition television (UHDTV) system with a 7,680 horizontal by 4,320 vertical pixel resolution and a 60 Hz frame rate. This system, which is called Super Hi-vision (SHV), is expected to serve the next generation of broadcasting services. We have just completed the world's first imaging equipment that is capable of capturing video at a full SHV resolution. In designing this equipment, we decided to develop three new devices, taking into account the camera performance and the ease of implementation. First, we developed a 33-megapixel CMOS image sensor. Its pixel size of 3.8 &mgr;m sq. retained the dynamic range of the sensor above 60 dB even with a 3-transistor pixel structure. Second, a fixed focal length lens was developed to create an adequate MTF right up to the limiting resolution of the sensor. Third, we developed a signal-processing device capable of handling 72 Gbps signals and cascading boards to expand the process. SHV images with a modulation of 20% at the Nyquist frequency were obtained by using these three key technologies.
In this paper, we present results of the investigation of the design and operation of CMOS active pixel sensors for detection of ultra-low light levels. We present a detailed noise model of APS pixel and signal chain. Utilizing the noise model, we have developed APS pixel designs that can achieve ultra-low noise and high responsivity. We present results from two test chips, that indicate (1) that less than 5 electrons of read noise is possible with CMOS APS by reducing the size of the pixel transistors, and (2) that high responsivity can be achieved when the fill-factor of the photodiode is reduced.
A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory with performance comparable to charge-coupled device (CCDs). This sensor is implemented using the industry-standard complementary metal-oxide semiconductor (CMOS) technology employed for nearly all microprocessors and memory chips and thus takes advantage of the rapid worldwide development of this technology. The CMOS active pixel sensor (APS) maintains the performance of CCDs regarding noise and quantum efficiency and offers unique advantages for ultra low power focal plane operation and integration of supporting electronics such as timing, control, clock, signal chains and analog-to-digital converters. This paper describes the technology for implementing a low power camera-on-a-chip.
Two 8 bit successive approximation analog-to-digital converters (ADC), an 8 bit single slope ADC and a 12 bit current mode incremental sigma delta ((Sigma) -(Delta) ) ADC have been designed, fabricated, and tested. The 20.4 micrometers and 40 micrometers pitch successive approximation test chip designs are compatible with active pixel sensors (APS) column parallel architectures. A 64 X 64 photogate APS with this ADC integrated on-chip was fabricated in a 1.2 micrometers N-well CMOS process and achieves 8 bit accuracy. A 1 K X 1 K APS with 11 micrometers pixels and a single slope ADC in each column was fabricated in a 0.55 micrometers N-well CMOS process and also achieves 8 bit accuracy. The successive approximation designs consume as little as 49 (mu) W at a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode (Sigma) -(Delta) ADC test chip is designed to be multiplexed among 8 columns in a semi-column parallel current mode APS architecture. It consumes 800 (mu) W at a 5 KHz conversion rate.
This paper describes a scalable, highly connected, 3D optoelectronic neural system that uses free-space optical interconnects with silicon-VLSI based hybrid optoelectronic circuits. The system design uses an efficient combination of pulse-width modulating optoelectronic neurons and pulse-amplitude modulating electronic synapses. A prototype system is built and applied to a simple classification problem. An optoelectronic testbench for evaluating learning algorithms suitable for the optoelectronic architecture is implemented. Future directions for the optoelectronic architecture are also discussed; these include limited interconnect neural systems and parallel weight loading that allow receptive fields of arbitrary sizes and connection multiplexing to be achieved.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.