KEYWORDS: Metrology, Optical proximity correction, Data modeling, Optical lithography, Signal to noise ratio, OLE for process control, Instrument modeling, Image analysis, Calibration, Metals
In the course of assessing OPC compact modeling capabilities and future requirements, we chose to investigate the interface between CD-SEM metrology methods and OPC modeling in some detail. Two linked observations motivated our study:
1) OPC modeling is, in principle, agnostic of metrology methods and best practice implementation.
2) Metrology teams across the industry use a wide variety of equipment, hardware settings, and image/data analysis methods to generate the large volumes of CD-SEM measurement data that are required for OPC in advanced technology nodes.
Initial analyses led to the conclusion that many independent best practice metrology choices based on systematic study as well as accumulated institutional knowledge and experience can be reasonably made. Furthermore, these choices can result in substantial variations in measurement of otherwise identical model calibration and verification patterns.
We will describe several experimental 2D test cases (i.e., metal, via/cut layers) that examine how systematic changes in metrology practice impact both the metrology data itself and the resulting full chip compact model behavior. Assessment of specific methodology choices will include:
• CD-SEM hardware configurations and settings: these may range from SEM beam conditions (voltage, current, etc.,) to magnification, to frame integration optimizations that balance signal-to-noise vs. resist damage.
• Image and measurement optimization: these may include choice of smoothing filters for noise suppression, threshold settings, etc.
• Pattern measurement methodologies: these may include sampling strategies, CD- and contour- based approaches, and various strategies to optimize the measurement of complex 2D shapes.
In addition, we will present conceptual frameworks and experimental methods that allow practitioners of OPC metrology to assess impacts of metrology best practice choices on model behavior.
Finally, we will also assess requirements posed by node scaling on OPC model accuracy, and evaluate potential consequences for CD-SEM metrology capabilities and practices.
Process-window (PW) evaluation is critical to assess the lithography process quality and limitations. Usual CD-based PW gives only a partial answer. Simulations such as Tachyon LMC (Lithography Manufacturability Check) can efficiently overcome this limitation by analyzing the entire predicted resist contours. But so far experimental measurements did not allow such flexibility. This paper shows an innovative experimental flow, which allows the user to directly validate LMC results across PW for a select group of reference patterns, thereby overcoming the limitations found in the traditional CD-based PW analysis. To evaluate the process window on wafer more accurately, we take advantage of design based metrology and extract experimental contours from the CD-SEM measurements. Then we implement an area metric to quantify the area coverage of the experimental contours with respect to the intended ones, using a defined “sectorization” for the logic structures. This ‘sectorization’ aims to differentiate specific areas on the logic structures being analyzed, such as corners, line-ends, short and long lines. This way, a complete evaluation of the information contained in each CD-SEM picture is performed, without having to discard any information. This solution doesn’t look at the area coverage of an entire feature, but uses a ‘sectorization’ to differentiate specific feature areas such as corners, line-ends, short and long lines, and thus look at those area coverages. An assessment of resist model/OPC quality/process quality at sub nm-level accuracy is rendered possible.
Assist features are commonly used in DUV lithography to improve the lithographic process window of isolated features under illumination conditions that enable the printability of dense features. With the introduction of EUV lithography, the interaction between 13.5 nm light and the mask features generates strong mask 3D effects. On wafer, the mask 3D effects manifest as pitch-dependent best focus positions, pattern asymmetries and image contrast loss. To minimize the mask 3D effects, and enhance the lithographic process window, we explore by means of wafer print evaluation the use of assist features with different sizes and placements. The assist features are placed next to isolated features and two bar structures, consistent with theN5 (imec iN7) node dimensions for 0.33NA and we use different types of off-axis illumination . For the generic iN7 structures, wafer imaging will be compared to simulation results and an assessment of optimal assist feature configuration will be made. It is also essential to understand the potential benefit of using assist features and to weigh that benefit against the price of complexity associated with adding sub-resolution features on a production mask. To that end, we include an OPC study that compares a layout treated with assist features, to one without assist features, using full-chip complexity metrics like data size.
Directed self-assembly of block copolymers is currently being investigated as a shrinking technique complementary to lithography. One of the critical issues about this technique is that DSA induces the placement error. In this paper, study of the relation between confinement by lithography and the placement error induced by DSA is demonstrated. Here, both 193i and EUV pre-patterns are created using a simple algorithm to confine two contact holes formed by DSA on a pitch of 45nm. Full physical numerical simulations were used to compare the impact of the confinement on DSA related placement error, pitch variations due to pattern variations and phase separation defects.
Source mask optimization (SMO) and double patterning technology (DPT) are considered key Resolution Enhancement
Technique (RET) enablers for scaling 2x nodes and beyond design rules, using existing 193 nm ArF technology prior to
EUV availability. SMO has been extensively shown to enlarge the process margin for critical layers in memory cells
and test patterns; however the best SMO flow for a large random logic area up to full-chip application has been less
explored. In this study, we investigated how the mask complexity in the source optimization impacts the final process
window on a random logic layout after DPT, and proposed a new source optimization approach.
Example used is a contact layer for 2x logic designs. The SMO source optimization is performed using the SRAM cells
with different mask complexities. These optimized sources are then evaluated based on a large-area random logic layout
after mask-only optimization. CD variation through process window is used as the metric for comparison. We found the
best result is obtained when the source is optimized with the full flexibility of the source and mask with freeform
SRAFs and minimal MRC constraints. The source optimized with this approach can reduce CD variation through
process window in the random logic without increasing its mask complexity.
Once a process is set-up in an integrated circuit (IC) manufacturer's fabrication environment, any drift in the proximity
fingerprint of the cluster will negatively impact the yield. In complement to the dose, focus and overlay control of the
cluster, it is therefore also of ever growing importance to monitor and maintain the proximity stability (or CD through
pitch behavior) of each cluster.
In this paper, we report on an experimental proximity stability study of an ASML XT:1900i cluster for a 32 nm poly
process from four different angles. First, we demonstrate the proximity stability over time by weekly wafer exposure and
CD through pitch measurements. Second, we investigate proximity stability from tool-to-tool. In a third approach, the
stability over the exposure field (intra-field through-pitch CD uniformity) is investigated. Finally, we verify that
proximity is maintained through the lot when applying lens heating correction.
Monitoring and maintaining the scanner's optical proximity through time, through the lot, over the field, and from toolto-
tool, involves extensive CD metrology through pitch. In this work, we demonstrate that fast and precise CD through
pitch data acquisition can be obtained by scatterometry (ASML YieldStarTM S-100), which significantly reduces the
metrology load.
The results of this study not only demonstrate the excellent optical proximity stability on a XT:1900i exposure cluster for
a 32 nm poly process, but also show how scatterometry enables thorough optical proximity control in a fabrication
environment.
IC manufacturers have a strong demand for transferring a working process from one scanner to another. Recently, a
programmable illuminator (FlexRayTM) became available on ASML ArF immersion scanners that, besides all the
parameterized source shapes of the earlier AerialTM illuminator (based on diffractive optical elements) can also produce
any desired freeform source shape. As a consequence, a fabrication environment may have scanners with each of the
illuminator types so both FlexRay-to-Aerial and FlexRay-to-FlexRay matching is of interest. Moreover, the FlexRay
illuminator itself is interesting from a matching point-of-view, as numerous degrees of freedom are added to the
matching tuning space.
This paper demonstrates how the upgrade of an exposure tool from Aerial to FlexRay illuminator shows identical
proximity behavior without any need for scanner tuning. Also, an assessment of the imaging correspondence between
exposure tools each equipped with a FlexRay illuminator is made. Finally, for a series of use-cases where proximity
differences do exist, the application of FlexRay source tuning is demonstrated. It shows an enhancement of the scanner
matching capabilities, because FlexRay source tuning enables matching where traditional NA and sigma tuning are
shortcoming. Moreover, it enables tuning of freeform sources where sigma tuning is not relevant. Pattern MatcherTM
software of ASML Brion is demonstrated for the calculation of the optimized FlexRay tuned sources.
This paper reports on a simulation study in which we compare different possibilities to find a litho solution for SRAM
and Logic for planar technology nodes between 28 nm and 20 nm, using 193 nm immersion lithography. At these nodes,
it becomes essential to include the layout itself into the optimization process. The so-called gridded layout style is an
attractive candidate to facilitate the printability of several layers, but the benefit of this style, as compared to less
restricted layout styles, is not well quantified for the various technology nodes of interest. We therefore compare it with
two other, less restricted, layout styles, on an identical (small) SRAM-Logic test chip. Exploring a number of paths in the
layout-style - litho-options search space, we try to quantify merits and trade-offs for some of the relevant options. We
will show that layout restrictions are really becoming mandatory for the technology nodes studied in this paper. Other
important enablers for these aggressive nodes are multiple patterning, the use of a local-interconnect layer, negative-tone
development, SMO and the use of optimized free-form illumination sources (from which we also include a few initial
wafer results).
The use of customized illumination modes is part of the pursuit to stretch the applicability of immersion ArF lithography. Indeed, a specific illumination source shape that is optimized for a particular design leads to enhanced imaging results. Recently, freeform illumination has become available through pixelated diffractive optical elements or through ASML's programmable illuminator system (FlexRayTM) allowing for virtually unconstrained intensity distribution within the source pupil. In this paper, the benefit of freeform over traditional illumination is evaluated, by applying source mask co-optimization (SMO) for an aggressive use case and wafer-based verification. For a 22-nm node SRAM of 0.099 and 0.078 μm2 bit cell area, the patterning of the full contact and metal layer into a hard mask is demonstrated with the application of SMO and freeform illumination. In this work, both pixelated diffractive optical elements and FlexRay are applied. Additionally, the match between the latter two is confirmed on wafer, in terms of critical dimension and process window.
Pellicles are mounted on the masks used in ArF lithography for integrated circuit manufacturing to ensure defect-free printing. The pellicle, a thin transparent polymer film, protects the reticle from dust. But, as the light transmittance through the pellicle has an angular dependency, the pellicle also acts as an apodization filter. In the current work, we present both experimental and simulation results at 1.35 numerical aperture immersion ArF lithography showing the influence of two types of pellicles on proximity and intra-die critical dimension uniformity (CDU). To do so, we mounted and dismounted the different pellicle types on one and the same mask. The considered structures on wafer are compatible with the 32-nm logic node for poly and metal. For the standard ArF pellicle (thickness 830 nm), we experimentally observe a distinct effect of several nm due to the pellicle presence on both the proximity and the intra-die CDU. For the more advanced pellicle (thickness 280 nm), no signature of the pellicle on proximity or CDU could be found. By modeling the pellicle's optical properties as a Jones Pupil, we are able to simulate the pellicle effects with good accuracy. These results indicate that for the 32-nm node, it is recommended to take the pellicle properties into account in the optical proximity correction calculation when using a standard pellicle. In addition, simulations also indicate that a local dose correction can compensate to a large extent for the intra-die pellicle effect. When using the more advanced thin pellicle (280 nm), no such corrections are needed.
In this paper we look into the litho and patterning challenges at the 22nm node. These challenges are different for
memory and logic applications driven by the difference in device layout. In the case of memory, very small pitches and
CDs have to be printed, close to the optical diffraction limit (k1) and resist resolution capability. For random logic
applications e.g. the printing of SRAM, real pitch splitting techniques have to be applied for the first time at the 22nm
node due to the aggressive dimensions of extreme small and compact area and pitch of SRAM bitcell. Common
challenges are found for periphery of memory and random logic SRAM cells: here the Best Focus difference per feature
type, limits the Usable Depth of Focus.
In current and next generation nodes lithography is pushed to low k1 lithography imaging regimes. A gridded design
approach with lines and cuts has previously been shown to allow optimizing illuminator conditions for critical layers in
logic designs.[1] The approach has shown good pattern fidelity and is expected to be scalable to the 7nm logic node. [2]
A regular pattern for logic makes the optimization problem straightforward if only standard cells are used in a chip.[3,4]
However, modern SOC's include large amounts of SRAM as well. The proposed approach truly optimizes both, instead
of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches.
The biggest problem in co-optimizing logic cells and SRAM bit cells is the orientation of critical layers. For SRAMs, the
gate and metal1 layers have lines in parallel directions, while in standard cells they are perpendicular. This would require
abandoning dipole illumination for the combined optimization, and at best using some form of quadrupole.
The alternative is to design the logic and SRAMs to be unified from the beginning. In this case, critical layer orientations
as well as pitches could be matched and each of the layers optimized for both functional sets of patterns. Choices of
patterns can be made to achieve DSMO (Design-Source-Mask-Optimization).
In the 28nm to 22nm logic nodes - with contacted pitches from 110nm to 90nm and metal1 pitches from 90nm to 70nm
- one of the questions to answer is when and for which layers double patterning is needed. The limit of single patterning
immersion lithography can only be explored through a smart combination of restricted designs and powerful sourcemask
optimization tools. In this paper a 28nm SRAM block with bit and word line periphery will be used to look at
choices for Design-Source-Mask-Optimization.
The use of customized illumination modes is part of the pursuit to stretch the applicability of immersion ArF lithography.
Indeed, a specific illumination source shape that is optimized for a particular design leads to enhanced imaging results.
Recently, freeform illumination has become available through pixelated DOEs or through FlexRayTM, ASML's
programmable illuminator system, allowing for virtually unconstrained intensity distribution within the source pupil.
In this paper, the benefit of freeform over traditional illumination is evaluated, by applying source mask co-optimization
(SMO) for an aggressive use case, and wafer-based verification. For a 22 nm node SRAM of 0.099 μm² and 0.078 μm2
bit cell area, the patterning of the full contact and metal layer into a hard mask is demonstrated with the application of
SMO and freeform illumination. In this work, both pixelated DOEs and FlexRay are applied. Additionally, the match
between the latter two is confirmed on wafer, in terms of CD and process window.
Pellicles are mounted on the masks used in ArF lithography for IC manufacturing to ensure defect-free printing. The
pellicle, a thin transparent polymer film, protects the reticle from dust. But, as the light transmittance through the pellicle
has an angular dependency, the pellicle also acts as an apodization filter.
In the current work, we present both experimental and simulation results at 1.35 NA immersion ArF lithography showing
the influence of two types of pellicles on proximity and intra-die Critical Dimension Uniformity (CDU). To do so, we
mounted and dismounted the different pellicle types on one and the same mask. The considered structures on wafer are
compatible with the 32 nm logic node for poly and metal. For the standard ArF pellicle (thickness 830 nm), we
experimentally observe a distinct effect of several nm's due to the pellicle presence on both the proximity and the intradie
CDU. For the more advanced pellicle (thickness 280 nm) no signature of the pellicle on proximity or CDU could be
found.
By modeling the pellicle's optical properties as a Jones Pupil, we are able to simulate the pellicle effects with good
accuracy. These results indicate that for the 32 nm node, it is recommended to take the pellicle properties into account in
the OPC calculation when using a standard pellicle. In addition, simulations also indicate that a local dose correction can
compensate to a large extent for the intra-die pellicle effect. When using the more advanced thin pellicle (280 nm), no
such corrections are needed.
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