Today novel RET solutions are gaining more and more attention from the lithography community that is facing new challenges in attempting to meet the new requirement of the SIA roadmap. Immersion, high NA, polarization, and mask topography, are becoming common place terminology as lithographers continue to explore these areas. Here with, we compare a traditional 6% MoSi based EAPSM reticle and a high transmission solution made of a SiON/Cr film stack. Insights into the manufacturability of high transmission material are provided. Test patterns have been analyzed to determine the overall impact of imaging performance when used with immersion scanners and polarized light. Some wafer results provide reliability of simulations, which are used to make further investigation on polarization and immersion effects.
Today novel RET solutions are gaining more and more attention from the lithography community that is facing new challenges in attempting to meet the new requirement of the SIA roadmap. Immersion, high NA, polarization, and mask topography, are becoming common place terminology as lithographers continue to explore these areas. Here with, we compare a traditional 6% MoSi based EAPSM reticle and a high transmission solution made of a SiON/Cr film stack. Insights into the manufacturability of high transmission material are provided. Test patterns have been analyzed to determine the overall impact of imaging performance when used with immersion scanners and polarized light. Some wafer results provide reliability of simulations, which are used to make further investigation on polarization and immersion effects.
Past work on mask topography has documented the effects of the topography on the aerial image intensity and on the responses of CD through defocus and image placement. Device performance, however, is limited by the statistical CD variation in the poly lines that form the logic and memory gates. We have developed a tool that combines fast, rigorous EMF calculations with Monte Carlo simulation to investigate the impact of mask topography on CD control. We have applied it to study the effects of mask topography on through-pitch CD
control in 6% EAPSM, AAPSM, and CPL reticles at 90-nm half-pitch design rules. The effects of the topography can be understood by examining the coefficients of the Fourier expansion of the near-field radiation pattern. The magnitude of the 3D effects is not correlated with the amount of mask topography but with the specific details of the Fourier coefficients that pass through the pupil. The topography mainly distributes the energy more evenly and introduces additional phase information. The best imaging results at tight pitch are obtained when the difference between the magnitudes of the two main Fourier coefficients that pass through the pupil is small and their phase difference is close to π. At larger pitches more diffracted orders will pass through the pupil, and the extra phase information from the additional orders will couple with aberrations in a reticle-dependent way and complicate overall RET choice.
Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds. The authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. Simulations on test structures have been calculated along with in photoresist simulations to predict the impact on process window capability. Test structures have been designed and fabricated into a functional test for evaluation. Process evaluations have been completed and exposure-defocus window calculated.
Today the industry is filled with intensity-balanced c:PSM and much more focus is being placed on innovative approaches such as CPL (and in conjunction with IML for Contacts) and tunable transmission embedded attenuating phase shift mask (TT-EAPSM). Each approach has its own merits and demerits depending on the manufacturing strategy and lithography performance required. Currently the only commercially available photomask blanks are different chrome thickness binary and 6% attenuating blanks using molybdenum-silicide, making the accessibility to alternate transmissions much more challenging. This paper investigates the mask manufacturability of a tunable transmission embedded attenuating phase shift mask. New film materials that are used in the mask blank manufacture are modeled, deposited and characterized to determine its ability to meet performance requirements. Sputtering models, by rate and gas component, determines film stacks with tunable transmissions and thicknesses. Chemical durability, etch selectivity and thickness are a few parameters of the films that have been characterized to enhance the manufacturability and process reliability of the masks. Lithography simulation models using measured optical properties were developed and test masks that include actual device designs were fabricated. Analysis of CD variation, pattern fidelity and process margin was performed using 3D mask simulation to understand the impact on 65nm design rules. Feasibility and performance of tunable transmission photomasks for use in design and lithography are verified. Moreover, the mask manufacturability and lithography performance is compared to other enhancement techniques and their merits presented.
The lithography prognosticator of the early 1980’s declared the end of optics for sub-0.5μm imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k1. Several authors have recently discussed manufacturing imaging solutions for sub-0.3k1 and the integration challenges. The requirements stated in the ITRS roadmap for current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will continue further for aggressive imaging solutions. Lithography and more importantly “imaging solutions” are driven by economics. The technology might be extremely innovative and “fun”, however, if it's too expensive it may never see the light of scanner. The authors have investigated and compared the capability of high transmission mask technology and image process integration for the 45nm node. However, the results will be graded in terms of design, mask manufacturability, imaging performance and overall integration within a given process flow.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/- 9nm1. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error factor (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as contacts. We have investigated the use of CPL mask technology for ArF contact hole imaging for sub-100nm contact imaging. The author's activities have been focused on the design, fabrication and integration of imaging technology. In this paper the author's emphasis will be on issues related to pattern layout, mask fabrication and image processing.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometries has forced device manufacturers to k1’s approaching 0.40. In this paper the authors will focus on the impact of mask exposure error factor (MEEF) through pitch for 120nm contacts with and without assist features. Experimental results show that although the addition of scatter bars improves depth of focus it has a negative effect on MEEF.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CPL) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. These new reticle technologies have many issues that are similar to simple binary masks. The authors have investigated the printability of defects in CPL mask technology. Programmed defects of various sizes and types have been simulated and printed for sub 100nm imaging. High resolution scanning electron microscopy has been used to characterize these defects and develop an understanding of size and type that prints. In this paper the authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
Despite very intense work since its re-discovery in the early 1990’s, phase-shift lithography is only in limited use today. The reason for its lack of wide spread use is not performance, for the benefits of phase-shift lithography are very well documented in the literature. The problem has been the greater complexity involved in making phase shirt masks, the inspection and repair of defects, and in dealing with phase-shift conflicts and other layout problems. The phase shift approach most commonly used is attenuated phase-shift. This is not very surprising in view of the fact that this phase-shift approach requires only one write-pass; and the inspection, repair and OPC are less difficult than the other phase-shift options. Despite these shortcomings, work on phase shift continues as we push resolution and extend the life of optical microlithography. The reason is that the alternatives, 157 nm and next-generation lithography, have its own set of issues. As we come to grips with the complexities of working in the vacuum region of the spectrum, we realize that 157 nm is likely to be delayed, and more expensive than originally thought. All next generation lithography options require a great deal of new infrastructure, with it associated coast. In this paper we report on a self-aligned rim phase shift approach. There have been reports of self-aligned rim phase shift approaches before, however our approach is unique in that it only requires one write-pass. This significantly simplifies the mask-making process.
Examining features of varying pitch imaged using phase-shifting masks shows a pitch dependence on the transmission best suited for optimum imaging. The reason for this deals with the relative magnitude of the zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and 180-degree phase-shifted regions. Subsequently, some of the diffraction orders are collected and projected to form the image of the object. Chromeless Phase-Shift Lithography (CPL) deals with using halftoning structures to manipulate these relative magnitudes of these diffraction orders to ultimately construct the desired projected image. A key feature of CPL is that with the ability to manipulate the diffraction orders, a single weak phase-shifting mask can be made to emulate any weak phase-shifting mask and therefore the optimal imaging condition of any pattern can be placed on a single mask regardless of the type of weak phase-shifter that produces that result. In addition, these structures are used to render the plurality of size, shape and pitch such that the formed images produce their respective desired size and shape with sufficient image process tolerance. These images are typically made under identical exposure conditions, but not limited to single exposure condition. These halftoning structures can be used exterior, as assist features, or interior to the primary feature. These structures can range in transmission from 0% to 100% and they can be phase-shifted relative to the primary features or not. Thus CPL deals with the design, layout, and utilization of transparent and semi-transparent phase-shift masks and their use in an integrated imaging solution of exposure tool, mask and the photoresist recording media. This paper describes the method of diffraction matching, provides an example and reviews some experimental data using high numerical aperture KrF exposure.
Examining features of varying pitch imaged using phase- shifting masks shows a pitch dependence eon the transmission best suited for optimum imaging. The reason for this deals with the relative magnitude of the zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and 180- degree phase-shifted regions. Subsequently, some of the diffraction orders are collected and projected to form the image of the object. chromeless Phase-Shift Lithography (CPL) deals with using half-toning structures to manipulate these relative magnitudes of these diffraction orders to ultimately construct the desired projected image. A key feature of CPL is that with the ability to manipulate the diffraction orders, a single weak phase-shifting mask can be made to emulate any weak phase-shifting mask and therefore the optimal imaging condition of any pattern can be placed on a single mask regardless of the type of weak phase- shifter that produces that result. In addition, these structures are used to render the plurality of size, shape and pitch such that the formed images produce their respective desired size and shape with sufficient image process tolerance. These images are typically made under identical exposure conditions, but not limited to single exposure condition. These half toning structures can be used exterior, as assist features, or interior to the primary feature. These structures can range in transmission from 0 percent to 100 percent and they can be phase-shifted relative to the primary features or not. Thus CPL deals with the design, layout, and utilization of transparent and semi- transparent phase-shift masks and their use in an integrated imaging solution of exposure tool, mask and the photoresist recording media. This paper describes the method of diffraction matching, provides an example and reviews some experimental data using high numerical aperture KrF exposure.
The exposure tool is a critical enabler to continue improving the packing density and transistor speed in the semiconductor industry. In addition to increasing resolution (improving packing density), a scanner is expected to provide tight linewidth control across the chip, ACLV (transistor speed). An important component of ACLV is lens aberrations. Recently techniques that allow the measurement in-situ of aberrations using Zernike coefficients have become available. We have measured the first 25 Zernike coefficients in two ASML PAS 500/700D DUV Step & Scan systems. The measured Zernikes are in agreement with PMI (Phase Measurement Interferometry) data collected at the lens manufacturer within 3.8 nm or less. We find good agreement between the variation of the Z5 (first order astigmatism) coefficient and the optimum focus offset between horizontal and vertical lines measured using FOCAL. There is also good agreement between Z5 and the linewidth difference between 160 nm horizontal and vertical lines with a 330 nm pitch. The lines were printed using an NA equals 0.68, (sigma) equals 0.70 on 3,800 angstrom of resist on top of an inorganic BARC. We find good correlation between the Z7 coefficient (first order coma) and linewidth variation across the slit. We also found that the effect of the aberrations as measured by linewidth range is a function of pitch. Linewidth range decreases as the duty ratio increases, reaching a minimum at a duty ratio of 1:1.44, and then increases again as the lines become isolated. This is surprising because these intermediate pitches also have the smallest focus-exposure window. We conclude that knowing the Zernike coefficients provides us with a very powerful tool to characterize our exposure tools. However to fully realize the benefit of this new tool we must improve the accuracy of our simulation tools.
The transition from aluminum/oxide to copper/low-k dielectric interconnect technology involves a variety of fundamental changes in the back-end manufacturing process. The most attractive patterning strategy involves the use of a so-called dual inlay approach, which offers lower fabrication costs by the elimination of one inter-level dielectric (ILD) deposition and polish sequence per metal layer. In this paper, the lithographic challenges for dual inlay, including thin-film interference effect, resist bulk effect, and optical proximity effects are reviewed. The use of attenuated phase shift (aPSM) reticles for patterning vias and trenches was investigated, and shown to provide adequate process margin by optimizing the photoresist and exposure tool parameters. Our results indicate that using appropriately sized attenuated phase shift technique increases the photospeed considerably and simultaneously improves the common process window with sufficient sidelobe suppression margin. The cost of ownership tradeoffs between an attenuated PSM I-Line process and a DUV binary process are discussed.
Due to the continuing decrease of the Rayleigh lithographic K1 factor used in advanced semiconductor technology, the non- linearity between designed and printed circuit images continues to increase. This increasing non-linearity has significant implications for the layout design rules with advanced technology. Recently, industry pundits have speculated that lithographic K1 factors can go far below current value. This paper aims to understand the impact of low K1 lithography upon a set of basic, company independent, layout design rules, the lambda based rules proposed by Mead and Conway. The results show that even with the use of aggressive optical proximity correction (OPC) techniques, significant changes in layout design rules will have to be made in order to extend lithographic capability to the low K1 regime.
It is well known that systematic within-chip dimension (CD) errors can strongly influence product yield and performance, especially in the case of microprocessors. It has been shown that this across chip linewidth variation (ACLV) dominates the CD error budge, and is comprised of multiple systematic and random effects, including substrate reflectivity, reticle CD errors, feature proximity, and lens aberrations. These effects have material, equipment, and process dependencies, with the results being that significant ACLV differences between nominally identical tools/processes can in some cases be observed. We present here a new analysis approach which allows for optimization of exposure/defocus conditions to minimize overall CD errors for a given process. Emphasis is on control of [(mean) + 3 sigma] of CD errors for a given exposure/defocus conditions. Input metrology data is obtained from electrical resistance probing, and data is presented for multiple 248 nm DUV processes and tools with CD ground rules ranging from 180 nm to 140 nm.
It is becoming increasingly clear that semiconductor manufacturers must rise to the challenge of extending optical microlithography beyond what is forecast by the current SIA roadmap. Capabilities must be developed that allow the use of conventional exposure methods beyond their designed capabilities. This is driven in part by the desire to keep up with the predictions of Moore's law. Additional motivation for implementing optical extension methods is provided by the need for workable alternatives in the event that manufacturing capable post-optical lithography is delayed beyond 2003. Major programs are in place at semiconductor manufacturers, development organization, and EDA software providers to continue optical microlithography far past what were once thought to be recognized limits. This paper details efforts undertaken by Motorola to produce functional high density silicon devices with sub-eighth micron transistor gates using DUV microlithography. The preferred enhancement technique discussed here utilizes complementary or dual-exposure trim-mask PSM which incorporates a combined exposure of both Levenson hard shifter and binary trim masks.
Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of- the-art 0.25 micrometer random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data improvements in reticle manufacturability, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.
An improved method is presented for the optimization of plasma deposited bottom inorganic anti-reflective coatings (ARCs). These ARCs have shown the capability to improve photolithography profess margins through reduction of substrate reflectivity while meeting integration issues. However, the ability to vary plasma ARC optical properties through deposition conditions has led to increased complexity of film stack optimization. We present simple but effective enhanced modeling methods for reducing the effort required to properly tune plasma ARC optical conditions and optimize complex films tacks incorporating these materials.
DUV scanning exposure systems have been steadily gaining market acceptance for the past five years, and soon, all major suppliers will offer 248-nm scanning tools. One of the major reasons for the emergence of this technology has been the purported improvement in critical dimension (CD) uniformity across the scanned field versus what can be realized in a full field stepper. Using high precision electrical resistance CD metrology, we have characterized the across field CD control capability of several DUV scanning tools and DUV steppers. Analysis is carried out through focus for multiple linetypes representing various orientations and nearest-neighbor proximities. Where possible, different NA/(sigma) combinations are examined as well. Surprisingly good full field sub-0.20 micrometers CD control is obtained even for 0.50 NA, and higher NA allows for non zero process latitude at 0.14 micrometers geometries. While it was initially anticipated that 193 nm ArF lithography would be required for 0.18 micrometers technology manufacturing, it has become apparent that 248 nm lithography will be employed for these groundrules, particularly for logic applications with predominantly semi-isolated features.
Submicron trench etching of single crystal silicon was studied in a single wafer magnetically enhanced reactive ion etching system. Trenches were etched with both HBr/SiF4/NF3/Iie/02 and HBr/SiF4 etch chemistries. A detailed comparison between the two etch chemistries revealed that acceptable trench profiles could be achieved with either chemistry. The HBr/SiF4/NF3IHeIO2 chemistry was found to be much more selective to the trench hard mask. However it also exhibited a higher density of " black silicon" in large trench areas. Trench profile silicon etch rate and hard mask selectivity were studied as a function of both magnetic field strength and wafer cooling with cooling producing the greater effect. Silicon loading was also found to affect the trench profiles that were obtained with either chemistry. Both of the etch processes exhibited a dependence of silicon etch rate on trench feature size. This dependence was found to become more pronounced as the trench depth increased. Analysis of transmission electron micrograph (TEM) data as well as preliminary electrical results indicate that very little crystal damage occurs with either etch chemistry.
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