The ever-shrinking lithography process window dictates that we maximize our process window, minimize process variation, and quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We present our effort to predict design-induced focus error hot spots based on prior knowledge of the wafer surface topography. This knowledge of wafer areas challenging the edge of our process window enables a constructive discussion with our design and integration team to prevent or mitigate focus error hot spots upstream of the imaging process.
This work describes the implementation and performance of AGILE focus corrections for advanced photo lithography in volume production as well as advanced development in IBM's 300mm facility. In particular, a logic hierarchy that manages the air gage sub-system corrections to optimize tool productivity while sampling with sufficient frequency to ensure focus accuracy for stable production processes is described. The information reviewed includes:
General AGILE implementation approaches; Sample focus correction contours for critical 45nm, 32nm, and 22nm applications; An outline of the IBM Advanced Process Control (APC) logic and system(s) that manage the focus correction sets; Long term, historical focus correction data for stable 45nm processes as well as development stage 32nm processes; Practical issues encountered and possible enhancements to the methodology.
The ever shrinking lithography process window requires us to maximize our process window and minimize tool-induced
process variation, and also to quantify the disturbances to an imaging process caused upstream of the imaging step.
Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects,
and design-induced topography. We quantify these effects and their interactions, and present efforts to reduce their harm
to the imaging process. We also present our effort to predict design-induced focus error hot spots at the edge of our
process window. The collaborative effort is geared towards enabling a constructive discussion with our design team, thus
allowing us to prevent or mitigate focus error hot spots upstream of the imaging process.
More sophisticated corrections of overlay error are required because of the challenge caused by technology
scaling faster than fundamental tool improvements. Starting at the 45 nm node, the gap between the matchedmachine-
overlay error (MMO) and technology requirement has decreased to the point where additional
overlay correction methods are needed. This paper focuses on the steps we have taken to enable
GridMapperTM, which is offered by ASML, as a method to reduce overlay error.
The paper reviews the basic challenges of overlay error and previous standard correction practices. It then
describes implementation of GridMapper into IBM's 300 mm fabrication facility. This paper also describes
the challenges we faced and the improvements in overlay control observed with the use of this technique.
Specifically, this paper will illustrate several improvements:
1. Minimization of non-linear grid signature differences between tools
2. Optimization of overlay corrections across all fields
3. Decreased grid errors, even on levels not using GridMapper
4. Maintenance of the grid for the lifetime of a product
5. Effectiveness in manufacturing - cycle time, automated corrections for tool grid signature changes
and overlay performance similar to dedicated chuck performance
As the Rayleigh equations already tell us, improvements in imaging resolution often come at the price of a depth-offocus
loss. Often we balance the resolution versus DoF dilemma without regard of the imaging layers location in the
overall film stack. E.g. often several via or metal layers are processed with the same optical settings despite facing
different amount of depth-of-focus requirements.
In actuality, however, substrate induced focus variation can vary greatly from layers at the bottom of a film stack to the
layers higher up in the film stack. In the age of super-low k1 lithography this variance needs to be taken into account on a
layer specific basis when evaluating the resolution versus DoF tradeoff.
We have studied substrate induced focus variation for a 45nm technology test-site as function of film stack sequence and
spatial frequency, combining various measurement techniques into an overall topography spectrum. These techniques
include data extraction from the exposure tools optical leveling sensor, a mechanical air gauge to calibrate the former
and interferometric profiling tools.
As a result, we can quantify our DoF requirement for a given layer and product and use this information to optimize our
process design on a layer-by-layer basis.
This work was performed by the Research Alliance Teams at various IBM Research and Development
Facilities
Depth of Focus (DOF) and exposure latitude requirements have long been ambiguous. Techniques range from scaling
values from previous generations to summing individual components from the scanner. Even more ambiguous is what
critical dimension (CD) variation can be allowed to originate from dose and focus variation. In this paper we discuss a
comprehensive approach to measuring focus variation that a process must be capable of handling. We also describe a
detailed methodology to determine how much CD variation can come from dose and focus variation. This includes
examples of the statistics used to combine individual components of CD, dose and focus variation.
Our case study experimentally gauges the defocus component induced by a step in the exposure field substrate, with
the edge of the step aligned parallel to the scanning slit. Such steps frequently occur at the border of different chiplets or
process monitors within one exposure field. A common assumption is that a step-and-scan imaging system can correct
for the majority of such topography, since the wafer is dynamically leveled under the static image plane as it is scanned.
Our results show that the range of defocus approaches about 85% of the actual step height and thus contributes
significantly to the overall focusing variance. This area on the wafer in which defocus can be observed extends by more
than 3mm to both sides of the step. In the same area a degradation of imaging fidelity can be observed in the form of
exaggerated proximity effects.
Two full-chip OPC approaches, a traditional rule-based approach and a more recent model-based approach are compared on DRAM applications using both ArF and KrF lithography, with off-axis illumination and phase shift masks. The similarities and differences between these two OPC approaches are compared in detail with selected one- and two-dimensional layout situations. Our results from the model-based approach show good line width control for one- dimensional structures and improved line-end printing for two-dimensional structures; however, results also show severe process window limitations for some layouts. The cause of the process window limitations with the model-based approach are discussed. To address the process window limitations in the model-based approach, a rule-based pre- correction was used to ensure adequate process window at deviated dose and focus conditions. With pre-correction combined with the model-based approach, our wafer data shows good correction quality and process window.
The continued downscaling of semiconductor fabrication ground rule has imposed increasingly tighter overlay tolerances, which becomes very challenging at the 100 nm lithographic node. Such tight tolerances will require very high performance in alignment. Past experiences indicate that good alignment depends largely on alignment signal quality, which, however, can be strongly affected by chip design and various fabrication processes. Under some extreme circumstances, they can even be reduced to the non- usable limit. Therefore, a systematic understanding of alignment marks and a method to predict alignment performance based on mark design are necessary. Motivated by this, we have performed a detailed study of bright field segmented alignment marks that are used in current state-of- the-art fabrication processes. We find that alignment marks at different lithographic levels can be organized into four basic categories: trench mark, metal mark, damascene mark, and combo mark. The basic principles of these four types of marks turn out to be so similar that they can be characterized within the theoretical framework of a simple model based on optical gratings. An analytic expression has been developed for such model and it has been tested using computer simulation with the rigorous time-domain finite- difference (TD-FD) algorithm TEMPEST. Consistent results have been obtained; indicating that mark signal can be significantly improved through the optimization of mark lateral dimensions, such as segment pitch and segment width. We have also compared simulation studies against experimental data for alignment marks at one typical lithographic level and a good agreement is found.
In the near future semiconductor manufacturing will continue to push minimum feature sizes towards and below dimensions of a tenth of a micron. The lithographic patterning process is particularly challenged to support this trend with an every-higher optical resolution. A variety of resolution enhancing technologies are currently developed to encounter this challenge. Processes with decreased wavelength, techniques using strong phase shifting and thin film imaging will compete in terms of optical performance and process cost-of-ownership over the next few years. This paper compares cost-of-ownership of major lithography options for memory wafer structuring at 120nm ground rules or below. ArF lithography, alternating phase shift masks and multi-layer resist techniques are the selected candidates for a process cost analysis. Their cost-of-ownership relevant characteristics are identified and quantified with focus on consistency. This is the basis for a cost analysis and will support a constructive discussion about process feasibility.
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