Mr. Bradley Morgenfeld Profile

Bradley Morgenfeld

at GLOBALFOUNDRIES

SPIE Involvement:

Author

Publications (15)

Proceedings Article | 23 March 2020 Presentation + Paper

Accuracy improvement in advance lithography focus control

Chris Hsu, Dongyue Yang, Cassidy Dineen, Xueli Hao, Young Ki Kim, Poya Hsu, Bradley Morgenfeld

Proceedings Volume 11327, 113270O (2020) https://doi.org/10.1117/12.2551904

KEYWORDS: Semiconducting wafers, Lithography, Critical dimension metrology, Diffraction, Scanners, Yield improvement, High volume manufacturing, Metrology, Wafer-level optics, Process control

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Proceedings Article | 20 March 2019 Presentation + Paper

Compact modeling of negative tone development resist with photo decomposable quencher

Ao Chen, Kar Kit Koh, Yee Mei Foong, Bradley Morgenfeld, Jun Chen, Sandra Lee, Xi Chen, Hesham Omar, Mu Feng, ChangAn Wang, Keith Gronlund, Jun Lang, James Guerrero, Yiqiong Zhao

Proceedings Volume 10961, 109610F (2019) https://doi.org/10.1117/12.2514784

KEYWORDS: Diffusion, SRAF, Photoresist processing, Calibration, Photo decomposable quencher, Semiconducting wafers, Process modeling, Performance modeling, 3D modeling, Error analysis

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Proceedings Article | 20 March 2018 Presentation + Paper

Line edge roughness reduction for 7nm metals

Zheng Chen, Steven McDermott, Christopher Ordonio, Ao Chen, Bradley Morgenfeld, Geng Han

Proceedings Volume 10587, 1058708 (2018) https://doi.org/10.1117/12.2297424

KEYWORDS: Line edge roughness, Etching, Lithography, Optical lithography, Photoresist processing, 193nm lithography

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Proceedings Article | 19 March 2018 Presentation

The challenge of multi-patterning lithography for contact layer in 7nm and beyond (Conference Presentation)

Wan-Hsiang Liang, Guanchen He, Yuan Zhou, Ming Hao Tang, Bradley Morgenfeld, David Conklin

Proceedings Volume 10586, 105860B (2018) https://doi.org/10.1117/12.2297504

KEYWORDS: Lithography, Optical lithography, SRAF, Source mask optimization, Extreme ultraviolet, Photomasks, Etching, Optical proximity correction, Electroluminescence, Double patterning technology

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When technology node transitions to 14nm and beyond, multi-patterning technique including litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) with optical lithography is required to achieve device scaling until extreme ultraviolet (EUV) comes into full production. Although LELE and SADP are widely used and well-studied for line-space layers, the challenge of contact layers still remains unknown. In addition, process window (PW) and pattern defects are often characterized with lithography printability only before 7nm. However, when the gate length is pushed to the limitation of immersion lithography, hard mask open etch (HMO) also needs to be studied along with lithography printability to further optimize overall patterning process window (PW). In this paper, we first studied several optical proximity correction (OPC) techniques such as source-mask optimization (SMO) and sub-resolution assist features (SRAF) to improve PW. We then characterized the patterning PW on several patterning defects including single-layer bridging, multi-layer bridging, missing contact, unlanded contact, and extra contact by tuning develop CD (DCD) and HMO CD (MCD). SMO such as illumination source and projection lens wavefront has been extensively used to enlarge depth of focus (DoF). Two different XY polarizations sources were optimized via SMO and were verified on silicon based on overlap process window and mask error enhancement factor (MEEF). Both sources have achieved <90nm lithography PW and <3 MEEF for the selected SRAM and logic designs. The effect of SRAF size on patterning PW were studied by obtaining DoF and exposure latitude (EL) post develop and post HMO. DoF was enlarged by 20nm when increasing SRAF size; however, EL was reduced by 6% post develop and by 2% only post HMO, suggesting patterning PW should be studied at post HMO instead of post develop. When characterizing multi-patterning PW, two types of defects need to be considered: type 1) single-layer bridging and missing contact driven by lithography only; type 2) multi-layer bridging, unlanded contact, and extra pattern driven by both lithography and HMO. Type 1 defects were studied by lithography printability from focus-exposure matrix for different targets (dense/semi-iso/iso) and maximum lithography PW was achieved by adjusting DCD. Type 2 defects were studied by adjusting both DCD and MCD (etch bias). Missing contact was improved by 20x and unlanded contact was improve by 5x when DCD was increased by 8%; however, multi-layer bridging was worsen by 10x, which can be improved by decreasing MCD by 8%. As a result, overall patterning PW can only be obtained by combining lithography PW and HMO optimization.

Proceedings Article | 27 March 2017 Presentation + Paper

Line end shortening and iso-dense etch bias improvement by ALD spacer shrink process

Rui Chen, Granger Lobb, Aleksandra Clancy, Bradley Morgenfeld, Shyam Pal

Proceedings Volume 10146, 101461D (2017) https://doi.org/10.1117/12.2260450

KEYWORDS: Atomic layer deposition, Etching, Optical lithography, Reactive ion etching, Semiconducting wafers, Semiconductors, Back end of line, Critical dimension metrology, Metals, Photomasks, Scanning electron microscopy

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SPIE Journal Paper | 2 May 2016

Intrafield overlay correction for illumination-based distortion

Michael Pike, Timothy Brunner, Bradley Morgenfeld, Nan Jing, Timothy Wiltshire

JM3, Vol. 15, Issue 02, 021406, (May 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.2.021406

KEYWORDS: Overlay metrology, Distortion, Scanners, Reticles, Image processing, Semiconducting wafers, Error analysis, Optical alignment, Photomasks, Calibration

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Proceedings Article | 15 March 2016 Paper

Patterned wafer geometry (PWG) metrology for improving process-induced overlay and focus problems

Timothy Brunner, Yue Zhou, Cheuk W. Wong, Bradley Morgenfeld, Gerald Leino, Sunit Mahajan

Proceedings Volume 9780, 97800W (2016) https://doi.org/10.1117/12.2218630

KEYWORDS: Semiconducting wafers, Metrology, Lithography, Overlay metrology, Silicon, Error control coding, Distortion, Optical lithography, Process control, Data modeling, Oxides, Silicon films, Thin films

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Proceedings Article | 18 March 2015 Paper

Intra-field overlay correction for illumination based distortion

Michael Pike, Timothy Brunner, Bradley Morgenfeld, Nan Jing, Timothy Wiltshire

Proceedings Volume 9426, 942613 (2015) https://doi.org/10.1117/12.2085887

KEYWORDS: Overlay metrology, Scanners, Distortion, Reticles, Semiconducting wafers, Optical lithography, Photomasks, Optical alignment, Lithographic illumination, Error analysis

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SPIE Journal Paper | 19 March 2012

Escaping death: single-patterning contact printing for 32/28-nm logic technology nodes

Bradley Morgenfeld, Ian Stobert, Ju Jin An, Massud Aminpur, Colin Brodsky, Alan Thomas, Henning Haffner, Martin Ostermayr, Hideki Kanai, Norman Chen

JM3, Vol. 11, Issue 1, 013010, (March 2012) https://doi.org/10.1117/12.10.1117/1.JMM.11.1.013010

KEYWORDS: SRAF, Printing, Optical proximity correction, Optical lithography, Critical dimension metrology, Etching, Logic, Photomasks, Semiconducting wafers, Model-based design

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Proceedings Article | 4 April 2011 Paper

Single exposure contacts are dead. Long live single exposure contacts!

Henning Haffner, Martin Ostermayr, Hideki Kanai, Chan Sam Chang, Bradley Morgenfeld, Jujin An, Meng Luo, Haoren Zhuang

Proceedings Volume 7974, 79740E (2011) https://doi.org/10.1117/12.879681

KEYWORDS: Optical proximity correction, Etching, Silicon, Double patterning technology, Oxides, Photomasks, Lithography, Logic, Printing, Semiconducting wafers

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Proceedings Article | 23 March 2011 Paper

Contact patterning strategies for 32nm and 28nm technology

Bradley Morgenfeld, Ian Stobert, Ju j An, Hideki Kanai, Norman Chen, Massud Aminpur, Colin Brodsky, Alan Thomas

Proceedings Volume 7973, 797319 (2011) https://doi.org/10.1117/12.879773

KEYWORDS: Optical lithography, SRAF, Critical dimension metrology, Etching, Semiconducting wafers, Model-based design, Photomasks, Lithography, Optical proximity correction, Double patterning technology

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SPIE Journal Paper | 1 January 2010

Lithographic qualification of new opaque MoSi binary mask blank for the 32-nm node and beyond

Gregory McIntyre, Michael Hibbs, Jaione Tirapu-Azpiroz, Geng Han, Scott Halle, Thomas Faure, Ryan Deschner, Bradley Morgenfeld, Sridhar Ramaswamy, Alfred Wagner

JM3, Vol. 9, Issue 01, 013010, (January 2010) https://doi.org/10.1117/12.10.1117/1.3295712

KEYWORDS: Photomasks, Binary data, Optical proximity correction, Lithography, Opacity, Semiconducting wafers, Data modeling, Electromagnetism, Calibration, Phase shifting

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Proceedings Article | 16 March 2009 Paper

Benefits and trade-offs of global source optimization in optical lithography

Kehan Tian, Azalia Krasnoperova, David Melville, Alan Rosenbluth, Dario Gil, Jaione Tirapu-Azpiroz, Kafai Lai, Saeed Bagheri, Chia-chen Chen, Bradley Morgenfeld

Proceedings Volume 7274, 72740C (2009) https://doi.org/10.1117/12.814305

KEYWORDS: Diffraction, Printing, Source mask optimization, Optical lithography, Resolution enhancement technologies, Photomasks, Semiconducting wafers, Lithographic illumination, Lithography, Manufacturing

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Proceedings Article | 16 March 2009 Paper

Contact mask optimization and SRAF design

Uwe Schroeder, Cyrus Tabery, Bradley Morgenfeld, Hideki Kanai

Proceedings Volume 7274, 727407 (2009) https://doi.org/10.1117/12.814814

KEYWORDS: SRAF, Photomasks, Critical dimension metrology, Printing, Lithography, Fiber optic illuminators, Optical proximity correction, Tolerancing, Data modeling, Optical lithography

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Proceedings Article | 1 April 2008 Paper

32 nm logic patterning options with immersion lithography

K. Lai, S. Burns, S. Halle, L. Zhuang, M. Colburn, S. Allen, C. Babcock, Z. Baum, M. Burkhardt, V. Dai, D. Dunn, E. Geiss, H. Haffner, G. Han, P. Lawson, S. Mansfield, J. Meiring, B. Morgenfeld, C. Tabery, Y. Zou, C. Sarma, L. Tsou, W. Yan, H. Zhuang, D. Gil, D. Medeiros

Proceedings Volume 6924, 69243C (2008) https://doi.org/10.1117/12.784107

KEYWORDS: Photomasks, Double patterning technology, Logic, Lithography, Etching, Optical lithography, Optical proximity correction, Immersion lithography, Printing, Image processing

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The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

Showing 5 of 15 publications

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