The improvement of overlay control in extreme ultra-violet (EUV) lithography is one of critical issues for successful mass production by using it. Especially it is important to improve the mix and match overlay or matched machine overlay (MMO) between EUV and ArF immersion tool, because EUV process will be applied to specific layers that have more competitive cost edge against ArF immersion multiple patterning with the early mass productivity of EUVL. Therefore it is necessary to consider the EUV overlay target with comparing the overlay specification of double patterning technology (DPT) and spacer patterning technology (SPT). This paper will discuss about required overlay controllability and current performance of EUV, and challenges for future improvement.
Advanced design nodes require more complex lithography techniques, such as double patterning, as well as advanced
materials like hard masks. This poses new challenge for overlay metrology and process control. In this publication
several step are taken to face these challenges. Accurate overlay metrology solutions are demonstrated for advanced
memory devices.
Overlay in lithography becomes much more challenging due to the shrink of device node and multi-patterning approach. Consequently, the specification of overlay becomes tighter, and more complicated overlay control methods like high order or field-by-field control become mandatory. In addition, the tight overlay specification starts to raise another fundamental question: accuracy. Overlay inaccuracy is dominated by two main components: one is measurement quality and the other is representing device overlay. The latter is because overlay is being measured on overlay targets, not on the real device structures. We investigated the following for accurate overlay measurement: optimal target design by simulation; optimal recipe selection using the index of measurement quality; and, the correlation with device pattern’s overlay.
Simulation was done for an advanced memory stack for optimal overlay target design which provides robustness for the process variation and sufficient signal for the stack. Robustness factor and sufficient signal factor sometimes contradicting each other, therefore there is trade-off between these two factors. Simulation helped to find the design to meet the requirement of both factors. The investigation involves also recipe optimization which decides the measurement conditions like wavelength. KLA-Tencor also introduced a new index which help to find an accurate measurement condition. In this investigation, we used CD-SEM to measure the overlay of device pattern after etch or decap process to check the correlation between the overlay of overlay mark and the overlay of device pattern.
In the HARC etching to form capacitor in DRAM fabrication, many essential requirements such as CD uniformity, vertical profile, process margin and etc. should be satisfied. The CD uniformity not only of the contact hole but also of the space between adjacent contact holes determines the distribution of the cell capacitance and leakage characteristics. The CD uniformity is mainly determined by the mask etching. Recently, it was found that the CD uniformity of the space between contact holes becomes worse along with the design rule shrinkage. And the worse CD uniformity comes from the tilted profile of the hard mask. Obtaining vertical contact profile is a traditional problem in HARC etching. To achieve large enough bottom CD fundamentally erodes side surface of the upper part of the contact and thus forms so called bowed profile. Serious bowed profile decreases the minimum space between adjacent contact holes and induces electrical leakage. In this paper, these issues and related challenges will be presented. And various approaches to understand the mechanism of the issues and to resolve them will be touched.
Recently, we found a peculiar acid induced defect on chemically amplified photo resist applied to sub-
30nm NAND Flash Memory. This defect is like a hole-pattern with about 1um diameter, and induced by
diffusion of acid which makes photoresist soluble in developer, even though photoresist is not exposed
with KrF. With some experiment results, we found out that HCl gas, by-product of high temperature oxide
which is contained inside voids between two gate lines diffuses into photoresist through high temperature
oxide from voids, makes photoresist soluble in developer, and eventually creates the hole-type defect on
photoresist. To prevent this defect, we can suggest some methods which are substitution of KrF
photoresist into I-line photoresist, modification of oxide deposition recipe to suppress by-product, and
applying of non-CAR (Chemically Amplification Resist) type KrF photoresist not sensitive to acid.
KEYWORDS: Optical lithography, Chemical mechanical planarization, Photomasks, Etching, Diffusion, Line width roughness, Bridges, Semiconductors, Astronomical imaging, Current controlled current source
While spacer is essential to separate the second lines from the first lines at negative tone spacer patterning technique,
Spacer brings side effects such as increase in process step as well as CD budget induced by spacer. To eliminate these
side effects, we have chosen the combination of photo resist as the first lines and developer soluble bottom ARC as the
second lines at negative tone spacer patterning technique. This process scheme consists of only two mask steps; one is
critical mask for the first lines in cell and peripheral cell, and another is non-critical mask for recess of the second lines
in cell area and removal of the second lines in peripheral area. By the diffusion of acid from photo resist into developer
soluble bottom ARC, developer soluble bottom ARC adjacent to photo resist of the first line is transformed into the
substance, which can be easily removed by developer dispensed after the second mask exposure. With the adoption of
developer soluble bottom ARC, we can expect to make progress in cost reduction at negative tone spacer patterning
technique.
Woo-Yung Jung, Guee-Hwang Sim, Sang-Min Kim, Choi-Dong Kim, Sung-Min Jeon, Keunjun Kim, Sang-Wook Park, Byung-Seok Lee, Sung-Ki Park, Hoon-Hee Cho, Ji-Soo Kim
KEYWORDS: Silicon, Etching, Carbon, Polymers, Optical lithography, Silicon carbide, Coating, Line width roughness, Double patterning technology, System on a chip
The spacer patterning technique (SPT) is well known as one of the methods expanding the resolution limit and mainly
useful for patterning line & space of memory device. Although contact array could be achieved by both spacer patterning
technique and double exposure & etch technique (DEET) 1, the former would be preferable to the latter by the issues of
overlay burden and resolution limit of isolated contact. The process procedure for contact array is similar to that for line
& space which involves the 1st mask exposure, etch, carbon polymer deposition, the 2nd mask exposure and etch step
sequentially. With SPT, it would be possible to realize contact array of 30nm half pitch including 30nm isolated contact
as well as line & space of 30nm half pitch.
Double patterning technique using spacer which can avoid CD (Critical Dimension) uniformity problem mainly caused by overlay issue is one of the methods that could be applied to apply to manufacturing of memory devices. Though double exposure and etch technology (DEET) has comparative advantage in the number of process steps, it is required to dramatically improve overlay performance of current exposure tools for the realization of manufacturing. In this study, negative type-double pattering technique using spacer has been developed as the best way for the application of NAND flash memory device from the view point of CD uniformity and the number of mask layers used to complete double patterning. Negative type-double patterning technique using spacer consists of subsequent steps such as formation of poly line, spacer on sidewall of poly line, SOG gap fill into space between poly lines, SOG etch back, removal of spacer, and finally hard mask etch. We have used amorphous carbon as a spacer material to easily remove spacer from poly lines and adopted SOG material to easily fill in space between poly lines. When negative type-double patterning technique using spacer is applied to NAND flash memory device, we can expect that k1 factor of about 0.14~0.20 could be accomplished successfully.
Double Exposure Technology (DET) is one of the main candidates for expanding the resolution limit of current lithography tool. But this technology has some bottleneck such as controlling the CD uniformity and overlay of both mask involved in the lithography process. One way to solve this problem and still maintain the resolution advantage of DET is using spacers. Patterning with a spacer not only expands the resolution limit but also solves the problems involved with DET. This method realizes the interconnection between the cell and peripheral region by "space spacer" instead of "line spacer" as usually used. Spacer process involves top hard mask etch, nitride spacer, oxide deposition, CMP, and nitride strip steps sequentially. Peripheral mask was additionally added to realize the interconnection region. With the use of spacers, it was possible to realize the NAND flash memory gate pattern with less than 50nm feature only using 0.85NA (ArF).
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.