Contact-hole patterning is even more challenging than line/space patterning because of the lower image contrast and smaller process window. To enable single exposure solution of 40-45nm half pitch contact-hole at this nearly resolvable limit of current 1.35NA ArF immersion lithography, negative tone development (NTD) process, source mask co-optimization (SMO) methodology and free-form source were explored in this study. The optimization of free form source and mask for NTD process was firstly carried out via Brion Tachyon SMOTM software. The wafer-level performance was then compared for different mask layout solutions and different mask types. A manufacture worthy process window was achieved for 40nm technology node Flash memory product through the combination of free-from source, SMO and NTD technologies. In the performance comparison for mask types, 6% HTPSM performed wider DoF and exposure latitude for all three pitch designs. But OMOG mask is superior to 6% HTPSM on mask and wafer CD uniformity. To further improve the overlapping process window, preserving the SMO layout solution as possible for the sparse environments and minimizing the SRAF writing errors were proposed as the two most critical tuning knobs.
In patterning the via-hole, uneven hole-size and missing-hole defects were identified through after etch inspection (AEI),
and these defects were characterized as yield killer since it led to electrical open. Through the after development
inspection (ADI) and AEI comparison, the uneven hole-size and missing-hole defects are attributed to the postdeveloped
satellite spots. The distribution of satellite spots always show a strong photo field map that is discovered to
correlate with the local pattern density in mask scribe lane. Apart from the possible modifications on pattern density in
the scribe lane by retooling the photo mask, this paper describes the work done in reducing the satellite defect. Several
development experiments including multiple wafer agitation cycles of dynamic puddle, multiple cycles of scanning rinse,
pre-wet before development, wafer rotation speed in rinse, wafer rotation speed in drying and advanced defect reduction
(ADR) function of track were carried out. The multiple cycles of scanning rinse coupling with the optimal wafer rotation
speed of rinse effectively suppresses the count of satellite spots. Pre spin dry in advance of the deionized water (DIW)
rinse to minimize the pH shock is also effective to reduce the defect count. Multiple cycles of development puddle and
scanning rinse have a synergy effect to lower defectivity up to complete suppression of satellite defect. To minimize the
throughput loss induced by the long development time, ADR is proposed as better candidate for fully eliminating the
satellite defect.
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