This paper presents an approach for data path allocation in high-level synthesis aiming at power reduction. In this approach, the register allocation and module allocation are performed in the same phase in polynomial time. The power consumption is reduced by minimizing the functional switching and switched capacitance of the implementation architecture. The experimental results confirm the viability and usefulness of the approach in minimizing power consumption while keeping the number of registers and interconnections to the optimal.
In this paper an ASIC implementation of a low cost speech recognition system for small vocabulary, 15 isolated word, speaker independent is presented. The IC is a digital block that receives a 12 bit sample with a sampling rate of 11.025 kHz as its input. The IC is running at 10 MHz system clock and targeted at 0.35 micrometers CMOS process. The whole chip, which includes the speech recognition system core, RAM and ROM contains about 61000 gates. The die size is 1.5 mm by 3 mm. The current design had been coded in VHDL for hardware implementation and its functionality is identical with the Matlab simulation. The average speech recognition rate for this IC is 89 percent for 15 isolated words.
KEYWORDS: Multiplexers, Data modeling, Computer aided design, Very large scale integration, Associative arrays, Data storage, Information operations, Optimization (mathematics), Silicon, Electronics engineering
With increasing design complexity of digital systems and small device features in sub-micron technologies, interconnection in the digital systems becomes more significant. In this paper, a technique for data path allocation aiming at interconnection optimization is presented. Not only can it optimize the interconnections of the design, but also it enables designers to balance the register cost and interconnection cost. Experimental test results show that this technique can produce good designs.
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