KEYWORDS: Design for manufacturing, Databases, Rule based systems, Semiconducting wafers, System identification, Visualization, Photomasks, Lutetium, Microelectronics, Design for manufacturability
In this paper we combined the hotspot pattern library and the rule-based scoring system into a modularized hotspot-checking rule deck running on an automatic flow. Several DFM (design for manufacture) properties criteria will be defined to build a “score board” for hotspot candidates. When hotspots in the input design are highlighted, the scoring system can identify whether a hotspot is a high risk hotspot or not, and define the severity of the hotspots by extracted DFM properties. The automatic flow will detect which layers are contained in the design then generate a modular rule deck with several corresponding hotspot check modules. The flow also takes snapshots of the high risk hotspots according to the score board automatically. After all the essential hotspot data is collected, the flow will automatically create an HTML-format report which has histograms of properties and overview graph that shows the distribution of hotspots. The aforementioned HTML report containing scored DFM properties and snapshots can help result-viewers to identify the high risk hotspots on the design quickly; namely, users can examine hotspots by snapshots without loading the whole design into layout viewer tools. By comparing the hotspot checking result with real defects from wafer data, a true hotspot’s values of DFM properties can be obtained. We believe this is helpful for users to improve their hotspot rules in accuracy.
The Mask Data Correctness Check (MDCC) is a reticle-level, multi-layer DRC-like check evolved from mask rule
check (MRC). The MDCC uses extended job deck (EJB) to achieve mask composition and to perform a detailed check
for positioning and integrity of each component of the reticle. Different design patterns on the mask will be mapped to
different layers. Therefore, users may be able to review the whole reticle and check the interactions between different
designs before the final mask pattern file is available. However, many types of MDCC check results, such as errors from
overlapping patterns usually have very large and complex-shaped highlighted areas covering the boundary of the design.
Users have to load the result OASIS file and overlap it to the original database that was assembled in MDCC process on
a layout viewer, then search for the details of the check results. We introduce a quick result-reviewing method based on
an html format report generated by Calibre® RVE. In the report generation process, we analyze and extract the essential
part of result OASIS file to a result database (RDB) file by standard verification rule format (SVRF) commands.
Calibre® RVE automatically loads the assembled reticle pattern and generates screen shots of these check results. All the
processes are automatically triggered just after the MDCC process finishes. Users just have to open the html report to
get the information they need: for example, check summary, captured images of results and their coordinates.
The mask composition checking flow is an evolution of the traditional mask rule check (MRC). In order to differentiate
the flow from MRC, we call it Mask Data Correctness Check (MDCC). The mask house does MRC only to identify
process limitations including writing, etching, metrology, etc. There still exist many potential errors that could occur
when the frame, main circuit and dummies all together form a whole reticle. The MDCC flow combines the design rule
check (DRC) and MRC concepts to adapt to the complex patterns in today’s wafer production technologies. Although
photomask data has unique characteristics, the MRC tool in Calibre® MDP can easily achieve mask composition by using
the Extended MEBES job deck (EJB) format. In EJB format, we can customize the combination of any input layers
in an IC design layout format, such as OASIS. Calibre MDP provides section-based processing for many standard verification
rule format (SVRF) commands that support DRC-like checks on mask data. Integrating DRC-like checking with
EJB for layer composition, we actually perform reticle-level DRC, which is the essence of MDCC. The flow also provides
an early review environment before the photomask pattern files are available. Furthermore, to incorporate the
MDCC in our production flow, runtime is one of the most important indexes we consider. When the MDCC is included
in the tape-out flow, the runtime impact is very limited. Calibre, with its multi-threaded processes and good scalability, is
the key to achieving acceptable runtime. In this paper, we present real case runtime data for 28nm and 14nm technology
nodes, and prove the practicability of placing MDCC into mass production.
Photolithography process is getting more and more sophisticated for wafer production following Moore’s law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers’ judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.
In state of the art integrated circuit industry for transistors gate length of 45nm and beyond, the sharp distinction between
design and fabrication phases is becoming inadequate for fast product development. Lithographical information along
with design rules has to be passed from foundries to designers, as these effects have to be taken into consideration during
the design stage to insure a Lithographically Friendly Design, which in turn demands new communication channels
between designers and foundries to provide the needed litho information. In the case of fabless design houses this
requirement is faced with some problems like incompatible EDA platforms at both ends, and confidential information
that can not be revealed by the foundry back to the design house.
In this paper we propose a framework in which we will try to demonstrate a systematic approach to match any
lithographical OPC solution from different EDA vendors into CalibreTM. The goal is to export how the design will look
on wafer from the foundry to the designers without saying how, or requiring installation of same EDA tools.
In the developed framework, we will demonstrate the flow used to match all steps used in developing OPC starting from
the lithography modeling and going through the OPC recipe. This is done by the use of automated scripts that
characterizes the existing OPC foundry solution, and identifies compatible counter parts in the CalibreTM domain to
generate an encrypted package that can be used at the designers' side.
Finally the framework will be verified using a developed test case.
Two aspects are critical when a new reticle type is introduced in a wafer fab: printability and reticle
inspection. In this study, we inspected 4 PSM reticles at the 45nm technology node, at P90, on the 5xx
TeraScanHR platform. We successfully inspected SL2+ reticles of the PSM type at P90. We forecast
that in a high volume 32nm node production environment, P72 SL2+ will address the inspectability
challenges associated with PSM masks. This is based on strict requirements for sensitivity on
contamination defects, inspectability, and cost of ownership, as when UMC addressed their wafer
printability issues.
By using two-photon autofluorescence (TPAF) and second harmonics generation (SHG), we imaged hepatocellular
carcinoma (HCC) biopsies from the human patients and compared them with the conventional histological biopsies. We
found that multiphoton microscopy may be used to obtain label-free images of liver tissues and may be developed into
an effective diagnostic tool for liver diseases.
The double dipole lithography (DDL) has been proven to be one of the resolution enhancement technologies for 45 nm
node. In this paper, we have implemented a full-chip DDL process for 45nm node using ArF immersion lithography.
Immersion exposure system can effectively enlarge the process DoF (depth of focus). Combining with dipole
illumination can help us to reach smaller k1 value (~0.31) and meet the process requirements of poly and diffusion
layers on 45nm node by using only 0.93 NA exposure tool. However, from a full-chip processing point of view, the
more challenging question should be: how to calibrate a good model from two exposure and decompose original design
to separate mask sets? Does the image performance achieve a production worthy standard? At 45nm node, we are
using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For DDL full-chip
processing, we need a robust application strategy to ensure a very tight CD control.
We implemented an integrated RET solution that combines DDL along with polarization, immersion system, and model
based OPC to meet full-chip manufacturing requirement. This is to be a dual-exposure mask solution for 45nm node - X-dipole exposure for vertical mask and horizontal for Y-dipole. We show a process design flow starting from the
design rule analysis, layout decomposition, model-based OPC, manufacturing reliability check, and then to the mask
data preparation. All of the work has been implemented using MaskWeaverTM geometry engine. Additionally, we
investigated printability for through-pitch line features, ASIC logic, and SRAM cell design patterns. Different circuit
layout needs dedicated special OPC treatment. To characterize the related process performance, we use mask
enhancement error factor (MEEF), process window (PW), and critical dimension uniformity (CDU) to analyze the
simulation data. Since we used the tri-tone Att-PSM, the mask making flow and spec was also taking into
consideration. The device electrical performance was examined for production feasibility. We conclude that the DDL
process is ready for 45nm node and is well within reach to be used on next generation production environment.
As semiconductor process technology moves to 65nm and beyond, RET (resolution enhancement technology)
becomes more and more important, especially in low k1 processes, where it is used frequently.
Currently, in the 65nm generation, the k1 is ~0.4 on a 0.85 NA exposure tool. However, the NA improvement of the
exposure tool cannot meet the schedule of generation movement very well. Low k1 technology must be applied on next
generation processes. For the 45nm generation, a 0.93 NA exposure tool is available currently and is used to achieve the
production criteria. Because the k1 value is quite low (~0.31), using traditional methods cannot satisfy process
requirements.
For metal layers of the 45nm generation, 55nm photo-resist CD (critical dimension) patterning of 130nm pitch is a
difficult goal on a 0.93 NA exposure tool. Traditional OAI (off-axis-llumination) (annular mode) cannot provide enough
image contrast for pattern printing. Customization of illumination mode is an approach on low k1 processes. Another one
is utilizing light source polarization to achieve resolution improvement. In this paper, we introduce different approaches
on 45nm metal patterning. The RET approach (C-quad. illumination mode with polarization) can provide enough image
contrast in pattern printing to solve process issues.
The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most
critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting
latent images in the wafer due to exposure of different design layouts. Accurate models can precisely
capture the proximity effects for the lithographic process and help RET engineers build the proper recipes
to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the
lithography environment that we want to model, and metrology data are collected for these geometries.
This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical
dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist
edge) data however model calibration requires EPE data for simulation. To work around this problem, only
symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements.
In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that
cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond.
The absence of 2D and asymmetric test structures in the calibration process would require models to
interpolate or extrapolate the EPE's for these structures in a real design.
In this paper we present an approach to extract the EPE information from both SEM images and contours
extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a
55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each
of these structures can be individually weighed according to the data variance. Model accuracy is then
compared to the conventional method of calibration using symmetrical data only. The paper also illustrates
the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to
errors compared to the conventional method.
As semiconductor process technology moves to smaller generations (65nm and beyond), the contact pattern printing
becomes the most difficult challenge in the lithography field. The reason comes from the smaller feature size and pitch of
contact/via pattern printing that is similar to 2D (two-dimensional) patterning. Contact and via patterns need better image
contrast than line/space patterns in pattern printing. Hence, contact/via printing needs a higher k1 value than others.
In 65nm generation experience, the k1 is ~0.44 on a 0.85 NA exposure tool. A larger NA exposure tool is expensive
and developed slower than the motivation of generation. Hence, the process is difficult to achieve by obtaining larger NA
exposure tools. The k1 requirement of 45nm (logic) contact pattering (minimum pitch: 140nm) is ~0.34 on a 0.93 NA
exposure tool that is available currently. RET (resolution enhancement technology) is necessary to achieve the difficult
process goal. Splitting pitch technology is an RET approach to solving 45nm contact pattering.
In this paper, we use a 2P1E (2 photo exposure and 1 etching) approach to meet our process requirements. The
original layout is split into dense pitch pattern and semi-iso to iso pattern parts by software. Utilizing strong OAI
(off-axis-illumination) on dense pattern part and weak OAI on semi-iso to iso pattern part can obtain better process
results.
In previous OPC model calibrations, most of the work was focused on how to calibrate a model for the best process
conditions. With process tolerance decreasing in coming lithography generations, it is increasingly important to be able
to predict pattern behavior through process window. Due to a low k1 factor that leads to a smaller process window, the
use of process window models is required for both optical proximity correction (OPC) and Lithography Rule Check
(LRC) applications to insure silicon success.
In this paper, we would try to calibrate multiple process window models. The resulting models will be verified and
judged using additional measurement data to demonstrate the quality.
Overlay variations between different layers in Integrated Circuits fabrication can result in poor circuit performance, even
worst it can cause circuit mal function and consequently affect process yield. Coupled with other lithographic process
variations this effect can be highly magnified. This leads to the fact that searching for interconnects hot spots should
include overlay variations into account. The accuracy of inclusion of the overlay variation effect comes at the expense of
a more complex simulation setup. Many issues should be taken into consideration including runtime, process
combinations to be considered and the feasibility of providing a hint function for correction.
In this paper we present a systematic approach for classification of interconnects durability through the lithographic
process, taking into account focus, dose and overlay variations, the approach also provides information about the cause
for the low durability that can be useful for building a more robust design.
This classification can be accessible at the layout design level. With this information in hand, designers can test the
layout while building up their circuit. Modifications to the layout for higher interconnects durability can be easily made.
These modifications would be extremely expensive if they had to be made after design house tape out.
We verify this method by showing real wafer failures, due to bad interconnect design, against interconnects' durability
classifications from our method.
As semiconductor process technology moves down below 90nm and 65nm, 193nm CPL (Chromeless Phase Lithography) technology becomes an important lithography strategy for process improvement on critical layers. In addition to the demand for very tight mask CD control, for a dry-etched process, there are two critical factors that can have significant impact on wafer CD control and window performance. They are etch-depth control (phase) through feature pitch and overall etching slope profile. Both affect image quality and the final overlapped process window. In this paper, we will study the effect of a 3D topology mask on the process window and wafer CD by making special 193nm CPL masks and printing them on 300mm wafers under a production-manufacturing environment. These masks had been specially designed with different sidewall angles and different etch depths (phase). There are 4 different quartz etch depths and 3 different sidewall angles for specially designed test patterns that are compatible with the 65nm technology node. They are printed on 300mm wafers by using a high NA ASML 193nm scanner and high contrast resist. In order to establish more effective specifications of phase and profile control on 193nm CPL between mask shops and wafer fabs, all AFM, wafer CD, and simulation results will be compared and correlated. By comparing the wafer CD and pattern profile on through focus conditions, we can understand the impact of phase and 3D mask profile on process performance.
Decreasing k1 factors require improved empirical models for the most critical challenge at 65nm node, contact holes especially. These requirements are reflected in the need for increasingly accurate lithography contour simulations. One of the major contributors to final OPC accuracy is the quality of the optical model. In this study, a new approach to the calibration of an optical model by using KIF will be proposed based upon the real through scanners and steppers of illumination distribution and implement to the OPC kernel.
Approaches to verify post-OPC designs for manufacturing have evolved from a number of separate inspection strategies. OPC decorations are verified by design rule or optical rule checkers, the reticle is verified by a reticle inspection system, and the patterned wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with very little data flowing between them.
Previously, we reported a new paradigm in design verification, moving the OPC verification from the design plane to the wafer plane where it really matters. The DesignScanTM system inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure calibration window, which can be up to twice as large as the process window. DesignScanTM first simulates the resist images at the nominal conditions (the best focus/exposure-F0E0) and compares them to pre-OPC design to detect unacceptable variations. Then it simulates resist images across the focus-exposure window and compares them to the best focus/exposure reference. Defect detection algorithms are applied to determine if any unacceptable variation in the pattern occurs within the nominal process window.
In this paper we will propose a new methodology on process window monitoring for OPC databases using DesignScan and report results for a chip. We will also report newly developed 2D defect detectors: line end shortening (LES) and interlayer overlap (ILO). New applications will be discussed and reported; such as, determination of the reticle target CD specification through process window simulation across a range of target CDs by biasing the post-OPC data by a few nanometers in both directions (+ and -). Pattern dependent reticle CD specifications are possible by identifying the weak structures.
For the 90nm-lithography node, understanding the impact of various reticle pinhole defects on wafer printability is essential to optimize wafer yield and to create the best quality reticle defect specification. In this study, a new programmed pinhole test reticle was designed by UMC, TCE and KLA-Tencor based on UMC's process requirements for its 193nm lithography. The reticle was manufactured and inspected on KLA-Tencor's high-resolution reticle inspection system in die to database mode by TCE. The reticle was then printed on a wafer by UMC to characterize the printability impact of programmed pinhole defects. The programmed pinhole test reticle, "193PTM", consists of two IC background patterns - poly gate and contact with programmed pinholes at various locations. The pinhole size ranges from 20nm to 75nm in 5nm increments on the wafer. By comparing the high-resolution pattern inspection results to the wafer print data, we have established the correlation and the appropriate mask specifications based on wafer application guidelines.
Off-axis illumination (OAI) has been shown as one of the most practical resolution enhancement techniques (RET) available for optical lithography. A customized off-axis illumination aperture filter (CIF) was designed to gain the benefits of OAI and keep the optical proximity effect (OPE) in a manage-able range for sub-0.18micrometers line and space patterns. The performance of the filter comparing with conventional, annular and quadruple illuminations in term of depth of focus, OPE, throughput, dose and power uniformity for both 0.18micrometers and 0.15micrometers NA Nikon KrF excimer laser stepper with a maximum partial coherence factor of 0.8 is presented in the paper. A brief description of the design principle of the filter is also given. A summarized conclusion on the weakness of the filter and possible improvements is also presented in the paper.
The resist dimples caused by the sidelobe effect are the unexpected by-products at printing 0.2-micrometer dense contact holes with attenuated phase-shift mask (PSM) and KrF laser stepper. We found that not only the printing bias and duty ratio but also the film thickness of the resist and the oxide layer underneath the resist affect the generation of the dimples. The 0.2-micrometer contact holes on 0.52-micrometer pitch were printed successfully without resist dimples by controlling the mentioned factors. Furthermore, the depth margin of the dimples was accessed in real etching process. The residual resist at dimples was 3150 Angstrom at least after development in order to against the etching process.
Several phase shift mask designs such as subresolution type, subresolution alternating type, outrigger type, and rim type for contact hole patterning were theoretically and experimentally evaluated in terms of their lithography performance. The various designed layouts which have the phase regions of manifold dimensions were simulated with lower coherent factor ((sigma) equals 0.3) and higher coherent factor ((sigma) equals 0.62). The detailed evaluation was made in terms of the log slope of the log image at nominal feature edge and side lobe effect of the intensity profile.
Output characteristics of a transverse discharge pumped atomic Ne laser (585.3 nm) using H2 as a penning partner has been studied. The laser energy is decreased with increasing the operating pressures. Lasing is terminated at 250 Torr. Peak intensity of the laser is saturated at high excitation rates (1 MW/cm3(DOT)atm). Mixing He as a buffer gas with Ne/H2 mixtures leads to depletion of the laser energy.
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