KEYWORDS: Data modeling, Deep learning, Education and training, Matrices, Gallium nitride, Diffusion, Simulations, Optical proximity correction, Performance modeling, 3D modeling
As layout schemes become increasingly complex for advanced technology nodes, challenges such as large edge placement error (EPE) and poor OPC convergence in optical proximity correction (OPC) can lead to significant yield losses. To overcome these issues, widely adopted strategies include layout re-targeting before OPC and mask feature modification after OPC for mask synthesis. The former entails adjusting the after-development inspection critical dimension (ADI CD) target of the original design layout. However, this process often relies on a time-consuming trial-and-error iterative approach to determine optimal sizing values for specific layouts. In recent years, machine learning techniques have shown promise in computational lithography, offering efficiency improvements. Leveraging the advantages of machine learning for guidance on layout re-targeting has the potential to reduce turnaround time. This paper presents a methodology that incorporates deep generative models into the layout re-targeting flow to propose proper sizing values for the layout of 3D NAND channel holes. Initially, we train two different deep generative models, namely Generative Adversarial Networks (GANs) and the Diffusion Model. These models are employed to infer sizing values for pre-OPC patterns through model prediction, utilizing input error data. Subsequently, the inferred sizing values are input into the design rule check (DRC) commands for polygon movement. Experimental results demonstrate that both deep generative models can predict layout sizing in the re-targeting flow, resulting in significantly improved accuracy of ADI CD and reduced turnaround time compared to the traditional trial-and-error approach.
The calibration of optical proximity correction (OPC) models has become increasingly challenging, especially when the behavior of photoresist on wafers cannot be adequately interpreted using conventional model terms assembled in a linear fashion. Additionally, fine-tuning such linearly separable physical components proves difficult due to evidence of nonlinear interactions among physical effects. In this study, we propose leveraging an advanced regression technique that progressively augments the linear model assembly with perturbative nonlinear neural network units the sharing same set of physics-inspired model terms as its base model, aiming to enhance model accuracy while maintaining stability. The research approach involves setting up initial models using conventional model calibration techniques, including optical model optimization and resist model optimization. Subsequently, we incorporate the Synopsys Advanced Regression (AR) neural network to identify essential non-linear interactions among modeling components. We selectively include these non-linear components into the existing linear model to capture on-wafer behavior. The entire process is designed to integrate seamlessly into the existing OPC production flow, ensuring a balance between model accuracy and efficiency. To evaluate the efficacy of the Synopsys AR method, we conduct tests on layers from 3D-NAND. The results demonstrate that this approach significantly reduces calibration costs due to its simpler calibration requirements.
Suboptimal layout geometries after optical proximity correction (OPC) might induce lithography hotspot, and result in degradation of wafer yield during integrated circuit (IC) manufacturing. Conventional hotspot correction methods have been widely conducted on post-OPC layout, such as rule-based or model-based hotspot fixing, but these methods might not completely solve hotspot issues due to the time-consuming process or model inaccuracy. Over the past of few years, the explosive growth of machine learning techniques has boosted the capability of computational lithography including hotspot detection and correction. In this paper, we focus on lithography hotspot correction with Generative Adversarial Network (GAN) to modify pattern shapes of hotspot and further improve lithographic printing of designed layout. The proposed approach first built a hotspot correction model based on different types of lithography rule check (LRC) hotspots, by training a pix2pix model to learn the correspondences between paired post-OPC layout image and after development inspection (ADI) contour image simulated from LRC tool. Then, we input hotspot-free contour image created from original hotspot into the deep learning model to generate supposedly hotspot-free mask image, and converted the mask image back into polygonal layout. Finally, mask layout with hotspot were partially replaced with predicted mask layout, and then examined with LRC simulation. Furthermore, we also implemented transfer learning for new hotspots captured from new design layout to expand the capability of our hotspot correction flow. Experimental results showed that this methodology successfully corrected lithography hotspots and significantly enhanced the efficiency of hotspot correction.
BackgroundAlgorithmic breakthroughs in machine learning (ML) have allowed increasingly more applications developed for computational lithography, gradually shifting focus from hotspot detection to inverse lithography and optical proximity correction (OPC). We proposed a pixelated mask synthesis method utilizing deep-learning techniques, to generate after-development-inspection (ADI) contour and mask feature generation.AimConventional OPC correction consists of two parts, the simulation model which predicts the expected contour signal, and the correction script that modifies the actual layout. With practicality in mind, we collected modeling wafer data from scratch, then implemented ML models to reproduce conventional OPC actions, mask to contour prediction, and design to mask correction.ApproachTwo generative adversarial networks (GANs) were constructed, a pix2pix model was first trained to learn the correspondences between mask image and paired ADI contour image collected on wafer. The second model is embedded into machine learning mask correction (ML-OPC) framework, output mask is optimized through minimizing pixel difference between design target and simulated contour.ResultsTwo different magnification SEM image datasets were collected and studied, with the higher magnification showing better simulator pixel accuracy. Supervised training of the correction model provided a quick prototype mask synthesis generator, and combination of unsupervised training allowed mask pattern synthetization from any given design layout.ConclusionsThe experimental results demonstrated that our ML-OPC framework was able to mimic conventional OPC model in producing exquisite mask patterns and contours. This ML-OPC framework could be implemented across full chip layout.
With the algorithmic breakthroughs in machine learning, increasingly more applications have been developed for computational lithography. In this paper, a pixelated mask synthesis method including After Development Inspection (ADI) contour and mask feature generation, was proposed by utilizing deep learning technique. Two Generative Adversarial Networks (GANs) were constructed, the first network was for mask to contour prediction, and the consecutive network was to perform design to mask correction. A pix2pix model was first trained to learn the correspondences between mask image and paired ADI contour image collected on wafer, thus the capability of printing prediction can be established. The well trained mask-to-contour model was then implemented as the simulator component of machine learning mask correction (ML-OPC) framework. Next, another unsupervised GAN formed the front-end of ML-OPC framework to synthesize mask patterns from any given design layout. Generated mask patterns were eventually optimized through minimizing pixel difference between design target and corresponding contour generated by mask-to-contour model. The experimental results demonstrated that our ML-OPC framework can mimic conventional OPC model to produce exquisite mask patterns and contours.
Background: As the design layout of integrated circuits (ICs) is continually scaling down, sub-resolution assist features (SRAF) have been extensively used in resolution enhancement technique applications to enhance lithography printing fidelity and widen the manufacturing process window (PW). With conventional SRAF insertion techniques, rule-based SRAF (RB-SRAF) and model-based SRAF (MB-SRAF) methods have since been widely adopted.
Aim: The typical RB-SRAF is an efficient method to generate SRAFs consistently for simple designs but cannot be optimized for multiple critical patterns or complex layout schemes. Although MB-SRAF is able to achieve better PW as well as reducing conflicts between placement rules and clean-up rules, many iterations for convergence and extremely high computational costs are required. The explosion of machine learning techniques could facilitate the complex processes of mask optimization, such as SRAF insertion.
Approach: Generative adversarial network was studied on a Via layer of advanced 3D NAND flash memory, by training target images and Inverse Lithography Technology (ILT) images of target patterns. GAN models, pix2pix, and CycleGAN, were first trained and then utilized to synthesize realistic ILT images.
Results: These ILT images were eventually translated to polygons of SRAF with simplification process and mask manufacturing rules check constraints. The simulation results demonstrate that CycleGAN approach can place SRAF with comparable performance to mask optimization (MO) result which was optimized by the Tachyon source-mask optimizer (SMO).
Conclusions: Methodologies of SRAF placement based on GANs were demonstrated in this paper. While traditional MO approach showed the best lithography performance, CycleGAN in particular was close behind and had much better performance than conventional RB-SRAF approach, whilst achieving good stability for different layout environments. Most importantly, the efficiency of SRAF insertion can be enhanced significantly through GANs.
Mask synthesis and correction flows are becoming increasingly complex in order to deal with increasingly smaller lithography, resist, and etch effects that also increase in importance with increasingly smaller feature sizes. Time-to-mask is also a significant factor in production environments which leads tapeout teams to adopt correction strategies that usually only address effects at the best process condition. As a result, users frequently find hotspots, or process failures, when performing a final lithography verification step using multiple process conditions. In many cases, under production pressure to decrease time-to-mask, tapeout teams choose to correct these hotspots in the fastest manner possible. Performing rule-based fixes to the post-correction layout is usually the fastest method available. This paper will explore using rule-based, post-correction hotspot fixes in a flow using pattern matching. Pattern matching will be used to cluster the post-correction patterns into similar types which will be fixed by different algorithms for each type. Further, pattern matching will be used to find all instances of each pattern to mark for fixing along any similar patterns that may have been missed by the lithography check, or those that received asymmetrical correction.
As the design layout of integrated circuits (ICs) is continually scaling down, sub-resolution assist features (SRAF) have been extensively used in resolution enhancement technique (RET) applications to enhance lithography printing fidelity and widen the manufacturing process window (PW). With conventional SRAF insertion techniques, rule-based SRAF (RB-SRAF) and model-based SRAF (MB-SRAF) methods have been widely adopted. The typical RB-SRAF is an efficient method to generate SRAFs consistently for simple designs, but cannot be optimized for multiple critical patterns or complex layout schemes. Although MB-SRAF is able to achieve better process window as well as reducing conflicts between placement rules and clean-up rules, many iterations for convergence and extremely high computational costs are required. The explosion of machine learning techniques could facilitate the complex processes of mask optimization, such as SRAF insertion. In this paper, generative adversarial network was studied on a Via layer of advanced 3D NAND flash memory, by training target images and Inverse Lithography Technology (ILT) images of target patterns. GAN models, pix2pix and CycleGAN, were first trained and then utilized to synthesize realistic ILT images. These ILT images were eventually translated to polygons of SRAF with simplification process and mask manufacturing rules check (MRC) constraints. The simulation results demonstrate that CycleGAN approach can place SRAF with comparable performance to mask optimization (MO) result which was optimized by the Tachyon Source-Mask Optimizer (SMO). Most importantly, the efficiency of SRAF insertion can be enhanced significantly through the generative adversarial network.
OPC (Optical Proximity Correction) has been employed for over decade to address local lithographic printing effects. With the intensive scaling down of the designs as well as the increasing complexity of layout routing, lithographic process is being pushed to its theoretical limit and it has led to continuously shrinking DoF (Depth of Focus). Complex OPC model components are hence included into optical lithography simulation to ensure tolerable CD (Critical Dimension) variation and sustainable DOF of concerned layouts. For example, very complicated segmentation needs to be applied in mask correction, which comes at the cost of long runtime and requires an effective approach to consolidate the adequacy of model components during the flow of correction parameter tuning. In this paper, an approach is demonstrated to improve the accuracy and efficiency of OPC parameter tuning for mask correction. The approach starts with analyzing the target points in post-OPC database to identify those intolerable variations, followed by a pattern similarity grouping for the above intolerable layouts. Then, a concern index is established based on the CD out-of-tolerance ratio, dissection and pattern type for prioritizing the problematic variations. Then the corrective parameters are accordingly optimized to reduce the variation on highly prioritized patterns. During the iteration flow of OPC parameter optimization, the combination of pattern grouping and concern index greatly reduces required optimization iterations for OPC recipe tuning and enhances OPC convergence.
To avoid the dramatically diminishing of lithography process window as the shrink of design rule, the implementation of process-aware optical proximity correction (PWOPC) has been indispensable. The conventional PWOPC is capable of reducing CD variation at off-focus-off-dose conditions for the worst hotspot but some new weak points might be generated due to over compensation from compromising with the worst hotspot. In this paper, a so-called “multiple-step process aware OPC”, was demonstrated for maintaining better process window for all hotspots via damascene metal layer in 43nm half-pitch design. Through isolating the hotspots from the chip layout, different CD tolerances can be applied for the various types of hotspots to avoid the conflicts between different requirements. Increased levels of CD-tolerance could be applied in the multiple-step PWOPC flow for the layout with a great number of weak points. The ultimate aim of the multiple-step PWOPC operation is maintaining sufficient process window for entire layout. The performance comparison was carried out among nominal OPC, conventional PWOPC and multiple-step PWOPC flows for contour CD within appropriate process window, turn around time of layout correction and CD distribution of hotspots.
The accuracy and efficiency of OPC (Optical Proximity Correction) modeling have become paramount important at the
low k1 lithography. However the accuracy of OPC model has to compromise with the efficiency of model calibration
and pattern correction, since the model accuracy is usually improved by using more kernels to represent the model but
the runtime of model setup and pattern correction also increase as kernel count increasing.
A novel decomposition of source kernel for OPC model calibration was presented in this study to maintain the model
accuracy and preserve the OPC runtime at acceptable level. Firstly, the source kernel was decomposed into multiple subsource
kernels and then the magnitude of electric field for each decomposed sub-source was modulated in frequency
domain. Finally, the resultant source can be the combination of many different sub-sources to represent the tool-specific
characteristics. The model accuracy, model stability and modeling runtime were compared among decomposed source,
ideal source and measured source models. The results showed modeling residual RMS error, predictive capability of
decomposed source can be reduced to be comparable to measured source and superior to the ideal source. As for the
modeling efficiency, the decomposed source is up to 5 times faster than the measured source but just few percentages
slower than the ideal source approach.
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