N2 node is introduced at 42nm poly pitch (CPP), 16 metal pitch (MP) by using 5 tracks (5T) cell height, single fin, and buried power rail (BPR). Due to the extreme cell height reduction, the patterning of the middle of line (MOL) become challenging. In this paper, two contact patterning schemes, staggered and aligned are presented and evaluated in terms of their impact on electrical performance on FinFET and Nanosheet. Simulations show that both options meet the performance target for N2. However, scaling at these dimensions also challenges the p-n separation between devices in a logic cell, which results in area penalty in complex cells. A novel device is introduced at N2 node, Forksheet, which shows higher performance and better area scaling at standard cell level compared to FinFET and NanoSheet.
KEYWORDS: Metals, Optical lithography, Fin field effect transistors, Extreme ultraviolet, Standards development, Silicon, Line edge roughness, Computer architecture, Process control
The targeted N3 technology node at IMEC is being redefined with respect to the poly pitch, as compared to the previous node definitions [1,2]. The overall industry trend of poly pitch scaling is slowing down, due to difficulties in keeping pace with device performance and yield issues. However, the metal pitch continues to scale down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore’s law. Here we present some of the options for the standard cell design that can enable an N3 technology node by using Design-Technology cooptimization (DTCO).
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