The new high numerical aperture (0.55NA) Extreme Ultraviolet Lithography (EUVL) machine has been developed by ASML, which is using an anamorphic projection system with the demagnification of 4× in x-direction and 8× in y-direction. Due to the unchanged 6-inch mask, 0.55NA EUVL reduces the exposure field size to half-field (26×16.5mm2). Therefore, the in-die stitching between two exposures might be needed for the applications requiring larger than half-field size. To enable High-NA EUV in die stitching, a complete mask data correction flow is needed. In this paper, we will investigate the in-die stitching effects and solution by using Ta-based dark field mask. We will show the impact of pattern types and decomposition rules on the stitching strategy, in addition to methods for correcting these stitching effects in optical proximity correction from an EDA perspective.
The new high numerical aperture (NA) Extreme Ultraviolet Lithography (EUVL) with a NA of 0.55 is being developed at ASML, which is using an anamorphic projection system with the demagnification of 4× in xdirection and 8× in y-direction. Compared to the traditional 0.33NA EUV scanner with full-field image size of 26 × 33mm2, 0.55NA EUVL reduces the exposure field size to half-field (26 × 16.5mm2), due to this 8× demagnification in y-direction and the reticle size remaining unchanged (six-inch square). Therefore, in-die stitching between two exposures is needed for the applications requiring larger than half-field size. To achieve in-die stitching in practical applications at advanced node, performing model based optical proximity correct (OPC) is an essential step. Therefore, a complete process modeling and OPC flow is required. To build an accurate OPC model, the interaction effects between two stitching fields require some special considerations, such as aerial image interaction, optical proximity effect among the stitching patterns, mask absorber reflection, black border proximity effect, as well as the stray light from the neighboring fields effect. All these effects must be captured by specific models. In this paper, we will investigate the in-die stitching effects and solutions through simulation and wafer data. Thus, to collect the wafer proof data, various stitching test patterns have been designed and placed on imec test masks, and the wafer data will be obtained on imec 0.33NA EUV scanner.
The ability to calibrate optical proximity correction (OPC) models accurately and efficiently is desired to minimize the lithography process development time. To compare layout features used for lithography process model calibration, the concept of optical similarity is introduced that is derived from the optical intensity used in OPC models. The optical similarity analysis is based on comparing contributions to the overall intensity from the different optical kernels. Optical similarity is applied in comparing individual features as well as in the analysis of pattern coverage between sets of features used in calibration of models for OPC. A method for selecting features for calibration from a larger set of features is described. A systematic approach to apply relative weights to different calibration features in order to improve model fit on complex verification data is also presented. This systematic approach to feature comparisons and pattern coverage derived from optical properties is demonstrated on numerous examples from production lithography. The methods presented here can improve the feature selection process for model calibration to ensure pattern coverage relative to full chip layout and hence improve the overall OPC model quality.
The physical process of mask manufacturing produces absorber geometry with significant deviations from the 90-deg corners, which are typically assumed in the mask design. The non-Manhattan mask geometry is an essential contributor to the aerial image and resulting patterning performance through focus. Current state-of-the-art models for corner rounding employ “chopping” a 90-deg mask corner, replacing the corner with a small 45-deg edge. A methodology is presented to approximate the impact of three-dimensional (3-D) EMF effects introduced by corners with rounded edges. The approach is integrated into a full-chip 3-D mask simulation methodology based on the domain decomposition method with edge to edge crosstalk correction.
The physical process of mask manufacturing produces absorber geometry with significantly less than 90 degree fidelity at corners. The non-Manhattan mask geometry is an essential contributor to the aerial image and resulting patterning performance through focus. Current state of the art models for corner rounding employ “chopping” a 90 degree mask corner, replacing the corner with a small 45 degree edge. In this paper, a methodology is presented to approximate the impact of 3D EMF effects introduced by corners with rounded edges. The approach is integrated into a full chip 3D mask simulation methodology based on the Domain Decomposition Method (DDM) with edge to edge crosstalk correction.
This study quantifies the impact of systematic mask errors on OPC model accuracy and proposes a methodology to reconcile the largest errors via calibration to the mask error signature in wafer data. First, we examine through simulation, the impact of uncertainties in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state of the art mask manufacturing data while other variable values are speculated, highlighting the need for improved metrology and communication between mask and OPC model experts. It is shown that the wafer simulations are highly dependent upon the 1D/2D representation of the mask, in addition to the mask sidewall for 3D mask models. In addition, this paper demonstrates substantial accuracy improvements in the 3D mask model using physical perturbations of the input mask geometry when using Domain Decomposition Method (DDM) techniques. Results from four test cases demonstrate that small, direct modifications in the input mask stack slope and edge location can result in model calibration and verification accuracy benefit of up to 30%. We highlight the benefits of a more accurate description of the 3D EMF near field with crosstalk in model calibration and impact as a function of mask dimensions. The result is a useful technique to align DDM mask model accuracy with physical mask dimensions and scattering via model calibration.
Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. Many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total critical dimension (CD) control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine via simulation the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state-of-the-art mask manufacturing data, and other variable changes are speculated, highlighting the need for improved metrology and communication between mask and optical proxmity correction model experts. The simulations are done by ignoring the wafer photoresist model and show the sensitivity of predictions to various model inputs associated with the mask. It is shown that the wafer simulations are very dependent upon the one-dimensional/two-dimensional representation of the mask, and for three-dimensional, the mask sidewall angle is a very sensitive factor influencing simulated wafer CD results.
Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. Many input variables
for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can
become significant. In this work, we examine via simulation, the impact of errors in the representation of
photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and communication between mask and OPC model experts. The simulations are done by ignoring the wafer photoresist model, and show the sensitivity of predictions to various model inputs associated with the mask. It is shown that the wafer simulations are very dependent upon the 1D/2D representation of the mask and for 3D, that the mask sidewall angle is a very sensitive factor influencing simulated wafer CD results.
Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models, which must balance accuracy demands with simulation runtime boundary conditions, rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. While certain system input variables, such as scanner numerical aperture, can be empirically tuned to wafer CD data over a small range around the presumed set point, it can be dangerous to do so since CD errors can alias across multiple input variables. Therefore, many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine with a simulation sensitivity study, the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD Bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and awareness.
KEYWORDS: 3D modeling, Data modeling, Photomasks, Calibration, Performance modeling, Semiconducting wafers, Optical proximity correction, Systems modeling, Panoramic photography, System on a chip
As mask feature sizes have shrunk well below the exposure wavelength, the thin mask of Kirchhoff approximation
breaks down and 3D mask effects contribute significantly to the through-focus CD behavior of specific features.
While full-chip rigorous 3D mask modeling is not computationally feasible, approximate simulation methods do
enable the 3D mask effects to be represented. The use of such approximations improves model prediction capability.
This paper will look at a 28nm darkfield and brightfield layer datasets that were calibrated with a Kirchhoff model
and with two different 3D-EMF models. Both model calibration accuracy and verification fitness improvements are
realized with the use of 3D models.
Sub-Resolution Assist Features (SRAFs) have been extensively used to improve the process margin for isolated and
semi-isolated features. It has been shown that compared to rule-based SRAFs, model-based placement of SRAFs can
result in better overall process window. Various model-based approaches have been reported to affect SRAF placements.
Even with model-based solutions, the complexity of two-dimensional layouts results in SRAF placement conflicts,
producing numerous challenges to optimal SRAF placement for each pattern configuration. Furthermore, tuning of
SRAF placement algorithms becomes challenging with varying patterns and sources [1-3].
Recently, pixelated source in optical lithography has become the subject of increased exploration to enable 22/20 nm
technology nodes and beyond. Optimization of the illumination shape, including free-form pixelated sources, has shown
performance gains, compared to standard source shapes [4-6]. This paper will demonstrate the influence of such
different free-form sources as well as conventional sources on model-based SRAF placement. Typically in source
optimization, the selection of the optimization patterns is exigent since it drives the source solution. Small differences in
the selected patterns produce subtle changes in the optimized source shapes. It has also been previously reported that
SRAF placements are significantly dependent on the illumination [1]. In this paper, the impact of changes in the design
and/or source optimization patterns on the optimized source and hence on the SRAF placement is reported. Variations in
SRAF placements will be quantified as a function of change in the free-form sources. Lithographic performance of the
different SRAF placement schema will be verified using simulation.
Immersion lithography is extending the lifetime of optical lithography by enabling numerical aperture (NA) greater than
unity. Along with scanner hardware improvements, modeling of hyper-NA lithography systems for optical proximity
correction (OPC) is also continuing to be necessary in improving photolithography capability. With the use of hyper-NA
immersion lithography and polarized illumination, the assumption of scalar optical pupil in optical system modeling may
no longer be valid. To fully describe the transmission of any polarization state through the optical system, Jones matrix is
necessary. It has been shown that Jones matrix can be described as a combination of apodization loss, birefringence,
diattenuation, scalar phase aberrations, and rotation effects. In this work, the impact of such effects on calibration and
accuracy of OPC models is characterized in terms of the model fit quality, model predictability, and changes to OPC
results.
As tolerance requirements for the lithography process continue to shrink with each new technology node, the
contributions of all process sequence steps to the critical dimension error budgets are being closely examined, including
wafer exposure, resist processing, pattern etch, as well as the photomask process employed during the wafer exposure.
Along with efforts to improve the mask manufacturing processes, the elimination of residual mask errors via pattern
correction has gained renewed attention. The portfolio of correction tools for mask process effects is derived from well
established techniques commonly used in optical proximity correction and in electron beam proximity effect
compensation. The process component that is not well captured in the correction methods deployed in mask
manufacturing today is etch. A mask process model to describe the process behavior and to capture the physical effects
leading to deviation of the critical dimension from the target value represents the key component of model-based
correction and verification. This paper presents the flow for generating mask process models that describe both shortrange
and long-range mask process effects, including proximity loading effects from etching, pattern density loading
effects, and across-mask process non-uniformity. The flow is illustrated with measurement data from real test masks.
Application of models for both mask process correction and verification is discussed.
KEYWORDS: Photomasks, Calibration, Data modeling, Process modeling, Optical proximity correction, Scanning electron microscopy, Semiconducting wafers, Electron beam lithography, Lithography, Reticles
With the push toward the 32nm node, OPC modeling must respond in kind with additional accuracy enhancements.
One area of lithographic modeling that has basically gone unchecked is mask fidelity. Mask linearity is typically built
into the OPC model since the calibration data contain this information, but mask pattern fidelity is almost impossible to
quantify for OPC modeling. Mask fidelity is the rounding and smoothing of the mask features relative to the post-OPC
layout intent, and there is no robust metric available to quantify these effects. With the introduction of contour-based
model calibration, mask fidelity modeling is possible. This work evaluates techniques to quantify mask modeling and
methods to gauge the accuracy improvement that mask fidelity modeling would project into the lithographic process
using contour-based mask model calibration.
In the application of model-based optical proximity correction (OPC) to a full chip layout, lithography simulators
require fast imaging algorithms to quickly obtain the critical dimensions (CDs) of the printed features. Model accuracy
is frequently traded-off for speed in order to shorten the computation time for full chip design. The sum-of-coherent
systems approximation represents the current standard for fast image computation. This approximation decomposes the
optical system response function in the Hopkins imaging equation into a sum of products of its eigenfunctions, or
kernels, via singular value decomposition. The partially-coherent optical imaging system is then represented as a sum of
images formed by coherently illuminated optical systems with transfer functions corresponding to the kernels of the
optical system response. The eigenvalues usually decay quickly, depending on the properties of the optical system.
Current models will typically use the first few dominant kernels since each additional kernel adds to the computational
time. However, there is no general guideline that indicates where to cut off the series in order to obtain the necessary
accuracy. In this paper, we propose a generally applicable heuristic for choosing the number of kernels.
We describe a few heuristics that show how to truncate the number of kernels that are included in a lithography model
calibration, resulting in a more efficient model for OPC treatment. The heuristics are based on various eigenvalue
measures such as the energy or the degree of coherence and express the CD error as a function of these measures. The
heuristics then show the number of kernels needed for a given accuracy.
Contact hole (CH) patterning for DRAM/Flash presents a key challenge for design rule below 50nm due to aggressive low-k1 conditions common in the leading DRAM/Flash memory designs. Combining optical proximity corrections (OPC) to the mask and optimized illumination has become an important part of production-worthy lithography processes for the 65nm node. At k1<0.31, both resolution and imaging contrast can become severely limited at NA<0.85 with some commonly available off-axis illumination sources. Hyper-NA and immersion lithography with polarized illumination capability can significantly increase the process latitude and is indispensable for manufacturing at sub-50nm design rule and beyond.
In this work, we describe our single-exposure approach for patterning Flash/DRAM contact-hole patterns with 120nm minimum pitch (and 60nm CH target CD). We use 6% attPSM dark-field mask both in simulations and for wafer exposures on ASML XT:1700i at NA=1.2. We begin with illumination source optimization using full vector high-NA simulation with (unpolarized and Y polarized illumination) a production resist stack and taking into account during the optimization all manufacturability requirements for the corresponding diffractive optical element (DOE) that produces the optimized source at the mask level. Using the optimized source, model-based OPC treatment was performed, which includes scattering bars (SB) placement using IMLTM technology and model-based CH feature biasing (MOPC) to achieve the optimum pattern printing fidelity in-focus and process latitude. To further increase of the depth of focus (DOF) for common process window (CPW) from 150nm to >250m, we used the focus scan (or, focus drilling) technique which is available in today's leading 193nm scanners.
Our results showed that, for the 120nm minimum pitch Flash CH patterns used, hyper-NA (NA>1) and immersion lithography (ASML XT:1700i platform was used in both simulation and scheduled for wafer exposures) is necessary, together with optimized illumination and model based OPC treatment, to achieve a yielding baseline process (common process window with DOF ~100nm). We also demonstrate that polarized illumination can significantly enhance the overall imaging performance, i.e., worst-case DOF can be increased >25% with optimized source, which is limited by the dense pitch CH arrays for this particular Flash CH pattern. With focus scan enabled for imaging, we show that the worst-case individual DOF can be easily doubled (from 150nm to >300nm) and EL at best focus (BF) remains >10% even at the largest focus range settings (400nm). The common process window decreased as focus scan range was increased, indicating that to maintain optimum common process window, MOPC treatment must be also performed under the same focus scan conditions. Patterning optimization (from illumination optimization to OPC) with focus scan enabled shows excellent promise as a single-exposure solution for patterning this 45nm Flash CH pattern and beyond.
The ability of a confocal microscope to inspect for defects on EUVL mask blanks has been investigated both experimentally and theoretically. A model was developed to predict the image contrast of confocal microscope. Measurements were made on PSL spheres and programmed multilayer defects using a Lasertec M1350 operating with 488 nm light. The images obtained of PSL spheres on both fused silica and multilayer-coated blanks are found to be accurately predicted with the model using no adjustable parameters. Good agreement is also demonstrated for the modeling of multilayer defects. Predictions are made for the expected increase in contrast at the shorter wavelength of 266 nm. Substrate roughness contributes to the "noise" which limits the sensitivity to small defects. The contrast fluctuations due to roughness have been modeled using a simple single surface approximation. The model has been validated with measurements on substrates with varying degrees of roughness. The contribution of mask roughness to the sensitivity of a 266 nm tool is estimated.
Defect detection sensitivity of a multi-beam confocal inspection system operating at a wavelength of 488 nm is characterized using experiments and image modeling. Experimental data on defect sensitivity are reported for programmed defects on mask substrates and blanks that are being developed for extreme ultraviolet lithography. The effects of sample surface roughness on the detection sensitivity and signal-to-noise levels are quantified. Theoretical analysis of confocal imaging of defects is in excellent agreement with measured defect images. Modeling is used to predict inspection sensitivity for defects commonly found on mask blanks.
The introduction of extreme ultraviolet (EUV) lithography into high volume manufacturing requires the development of a new mask technology. In support of this, Intel Corporation has established a pilot line devoted to encountering and eliminating barriers to manufacturability of EUV masks. It concentrates on EUV-specific process modules and makes use of the captive standard photomask fabrication capability of Intel Corporation. The goal of the pilot line is to accelerate EUV mask development to intersect the 32nm technology node. This requires EUV mask technology to be comparable to standard photomask technology by the beginning of the silicon wafer process development phase for that technology node. The pilot line embodies Intel's strategy to lead EUV mask development in the areas of the mask patterning process, mask fabrication tools, the starting material (blanks) and the understanding of process interdependencies. The patterning process includes all steps from blank defect inspection through final pattern inspection and repair. We have specified and ordered the EUV-specific tools and most will be installed in 2004. We have worked with International Sematech and others to provide for the next generation of EUV-specific mask tools. Our process of record is run repeatedly to ensure its robustness. This primes the supply chain and collects information needed for blank improvement.
In this work, we are reporting on a lithography-based methodology and automation in the design of Program Defect masks (PDM’s). Leading edge technology masks have ever-shrinking primary features and more pronounced model-based secondary features such as optical proximity corrections (OPC), sub-resolution assist features (SRAF’s) and phase-shifted mask (PSM) structures. In order to define defect disposition specifications for critical layers of a technology node, experience alone in deciding worst-case scenarios for the placement of program defects is necessary but may not be sufficient. MEEF calculations initiated from layout pattern data and their integration in a PDM layout flow provide a natural approach for improvements, relevance and accuracy in the placement of programmed defects. This methodology provides closed-loop feedback between layout and hard defect disposition specifications, thereby minimizing engineering test restarts, improving quality and reducing cost of high-end masks. Apart from SEMI and industry standards, best-known methods (BKM’s) in integrated lithographically-based layout methodologies and automation specific to PDM’s are scarce. The contribution of this paper lies in the implementation of Design-For-Test (DFT) principles to a synergistic interaction of CAD Layout and Aerial Image Simulator to drive layout improvements, highlight layout-to-fracture interactions and output accurate program defect placement coordinates to be used by tools in the mask shop.
The printability of both amplitude and phase defects has been investigated in proximity to absorber lines with widths corresponding to the 45 nm and 32 nm nodes. The single surface approximation was used to simulate defects within the multilayer coating. The printability of Gaussian phase defects was simulated versus width and height and location with respect to the absorber line. For narrow defects the worst location was found to be next to the absorber line, while wide defects had the greatest effect when centered under the absorber. A uniform flare was found to have little effect on the critical defect size. The results of these simulations are aimed at defining the critical defects for EUVL masks designed for the 32 nm node.
The use of alternating phase shift masks (Alt-PSMs) for poly gate patterning is becoming a well-established method for reducing gate critical dimension (CD) and variability. The application of alt-PSM for other device layers and for improving resolution (minimum pitch) is less developed due to more complex layouts, more stringent mask constraints and cost of ownership restrictions. Resolution of contact pairs and nested contacts is found to be improved using alt-PSM compared to embedded PSMs (EPSMs). To improve the process window of semi-nested and isolated contacts, sub-resolution phase-shifted assist features are employed on the mask. Square assist features, rather than rectangular assist features, are used to reduce mask fabrication requirements as one can use a larger minimum assist feature dimension. Because of high mask error enhancement factors (MEEFs), assist features with dimensions as large as 75% of the nominal contact size can be used without patterning on the wafer. Compared to using alt-PSM for poly gate patterning the use of alt-PSM for tight pitch patterning places additional constraints on mask manufacturing. The smaller phase regions intrinsic to tight pitch patterning result in tighter phase uniformity and mask defect requirements.
Inspection of extreme ultraviolet (EUV) lithography masks requires reflected light and this poses special challenges for inspection tool suppliers as well as for mask makers. Inspection must detect all the printable defects in the absorber pattern as well as printable process-related defects. Progress has been made under the NIST ATP project on "Intelligent Mask Inspection Systems for Next Generation Lithography" in assessing the factors that impact the inspection tool sensitivity. We report in this paper the inspection of EUV masks with programmed absorber defects using 257nm light.
All the materials of interests for masks are highly absorptive to EUV light as compared to deep ultraviolet (DUV) light. Residues and contamination from mask fabrication process and handling are prone to be printable. Therefore, it is critical to understand their EUV printability and optical inspectability. Process related defects may include residual buffer layer such as oxide, organic contaminants and possible over-etch to the multilayer surface. Both simulation and experimental results will be presented in this paper.
Intel will start high volume manufacturing (HVM) of the 65nm node in 2005. Microprocessor density and performance trends will continue to follow Moore's law and cost-effective patterning solutions capable of supporting it have to be found, demonstrated and developed during 2002-2004. Given the uncertainty regarding the readiness and respective capabilities of 157nm and 193nm lithography to support 65nm technology requirements, Intel is developing both lithographic options and corresponding infrastructure with the intent to use both options in manufacturing. Development and use of dual lithographic options for a given technology node in manufacturing is not a new paradigm for Intel: whenever introduction of a new exposure wavelength presented excessive risk to the manufacturing schedule, Intel developed parallel patterning approaches in time for the manufacturing ramp. Both I-line and 248nm patterning solutions were developed and successfully used in manufacturing of the 350nm node at Intel. Similarly, 248nm and 193nm patterning solutions were fully developed for 130nm node high volume manufacturing.
For optical inspection of Extreme Ultraviolet Lithography (EUVL) masks using Deep Ultraviolet (DUV) light, contrast from reflected light is used to form the image of the mask and detect the defects. The inspectability of a patterned mask depends on the optical properties, surface conditions and thickness of absorber and buffer layer. The issue in EUVL mask inspection is the relatively low image contrast in the inspection tool because both the EUV-reflective and EUV-absorbing regions reflect DUV light. The need of a buffer layer to protect the multilayer (ML) reflector during mask processing and defect repair necessitates two inspections for a patterned mask: one with the buffer layer on to find the defect for repair and one with the buffer layer removed to qualify a final mask. Since the ML appears bright at DUV inspection wavelengths, the buffer layer is also chosen to give high reflectivity. Therefore, the absorber reflectivity must be low enough to provide high image contrast and to avoid the edge interference effect. Recently, we have developed a surface treatment process to reduce the reflectivity of absorber layer and result in a DUV contrast approaching 90 percent. This greatly improves the optical inspectability of EUVL mask to a level similar to conventional transmission mask. In this paper, we describe the overall EUVL mask inspection strategy and present a comprehensive discussion on mask optimization in materials selection and modification for high inspectability. We report the reflectivity of Mo-Si multilayer, buffer layers using SiO2 and Ru, and absorber layers of Cr and TaN. We will demonstrate with DUV inspection images of the optimized EUVL masks that the image contrast and quality from reflected light are close to those of conventional photo-masks with transmitted light. This greatly enhanced EUVL mask inspectability will increase defect detectability for inspection tools and simplify image rendering in die-to-database inspection.
The industry traditionally uses a single number, the change in the printed line width, to quantify mask defect printability. The measurement of this change is done in the direction perpendicular to a main feature, usually a line. We often ignore the extent of the printed defect parallel to the line even though our intuition tells us it will also contribute to the impact of the defect. If the lithography resolution improves the defects will be better resolved and their printed image will more closely approximate the shape of the defect. This leads to an increase in the line width change of the defect. This leads to very high defect printability in the case of high k1 lithographies, such as extreme ultraviolet lithography (EUVL). Thus, traditional methods of quantifying printability will lead to very stringent mask defect specs for capable lithographies with low mask error enhancement factors. We present an analysis of the electrical impact of gate layer defects and derive an expression that takes the printed defect extent in both directions into consideration. Since the printed defect extent parallel to the line depends on the lithography resolution and, therefore, the lithography process k1 factor, the electrical impact of the mask defect can be shown to be dependent on k1. Finally, we will present a mask defect criterion with explicit k1 dependence and discuss its implication to EUVL.
Embedded phase shift masks (ePSM) are critical to patterning the contact layer of integrated circuit devices of 130 nm technology node and beyond. Required ePSM inspection methodologies needed for the successful manufacturing of a “defect-free” ePSM are discussed in this study. We present an analysis of different inspection schemes for handling inspection system optical signals from tritone ePSM. Programmed defect ePSM plates with 6% shifter material transmission fabricated for 248 nm and 193 nm wafer exposures are characterized by metrology tools and inspected on existing optical mask inspection systems. Capture rates for various defect types are analyzed. The results of inspection sensitivity analysis are also compared with the defect specifications based on a defect printability simulation study. Key challenges ternary ePSM inspection are also discussed
In an attempt to narrow the choice for an absorber used in EUV masks, different materials are being evaluated. These materials need to meet the absorber requirements of EUV absorbance, emissivity, inspection, and repair, to name a few. We have fabricated masks using Cr absorbers. The absorber stack consists of a repair buffer of SiON and a conductive etch stop of Cr sandwiched between the SiON repair buffer film and the Mo/Si multilayer mirror deposited on a Si wafer. However, to increase the process latitude, the Cr etch stop needs to be removed from the stack, in particular for mask repair. The absorber layer was patterned using commercial DUV resist and the pattern was transferred using reactive ion etching (RIE) with halogen-based gases. Completed masks exhibited negligible shift in the centroid wavelength of reflectivity and less than 2% loss in peak reflectivity due to mask patterning. Completed masks were exposed at Sandia National Laboratories' 10X EUV exposure system and equal lines and spaces down to 80 nm were successfully printed. The masks were also imaged in a microscope with 248 nm wavelength, and the focused ion beam repair selectivity to the buffer layer (SiON) was established. The paper summarizes the mask fabrication process, EUV printability, mask repair, inspection and emissivity for EUVL masks with Cr absorber.
Inspection and repair of defects represent some of the challenges for the fabrication of 'defect-free' alternating phase-shift masks needed for performance improvements in patterning the polysilicon gate layer of integrated circuit devices. Inspection, metrology, repair, and printability of defects on dark-field alternating phase-shift masks used in dual exposure processes for polysilicon gate layer patterning are discussed in this study. The impact of phase and chrome defects on photoresist features printed at an exposure wavelength of 248 nm is evaluated and compared to the defect signals measured on a mask inspection tool operating at 364 nm. Experimental data on printability and inspection of programmed glass defects with several different phase errors as well as programmed chrome defects are compared to simulations. The effects of the exposure tool focus conditions on phase defect printability are discussed in detail. Phase defect contrast enhancement mechanisms that may enable improvements in phase defect detection during mask inspection using conventional inspection tools are also addressed. Finally, successful repairs of real glass bump defects are demonstrated.
While the use of phase shift masks can improve CD control and allow the patterning of smaller poly gate features, it also introduces new error terms for overlay. Four error terms are discussed: increased sensitivity of image placement to coma-type aberrations, image placement shifts resulting form phase errors, image placement shifts resulting from intensity imbalance between zero and 180 degrees shifter regions, and phase shift mask to trim mask overlay issues. These overlay issues become increasingly important for lower k1 patterning. Likewise, phase defect printability is magnified for lower k1 patterning, increasing the requirements for phase shift mask inspection and repair.
The final qualification of masks for extreme ultraviolet (EUV) lithography may require defect inspection utilizing EUV radiation. To properly address inspection of masks for the 0.07-micrometer technology generation targeted by EUV lithography, the overall defect sensitivity requirements and scaling trends in inspection of patterned masks are discussed. To achieve the data acquisition rates of several hundred megapixels/sec required during inspection of 0.07-micrometer technology masks and to maintain light intensities below the damage threshold of mask materials, simultaneous acquisition of the inspection signal from multiple pixels on the mask, rather than the serial pixel data collection currently used in many mask inspection tools, will become necessary. The high data rates needed for future mask inspection technologies impose requirements on the minimum pulse repetition rate of the light source used in the inspection and influence the EUV mask inspection system design options. EUV light sources that either produce continuous-wave radiation or operate at pulse repetition rates of at least 10 - 100 kHz will be needed for mask inspection relevant to EUV technology, assuming that data from 104 or more pixels can be measured in parallel. The average EUV light source power requirements for an at- wavelength, bright-field EUV mask inspection system are estimated to be on the order of 1 W. The basic technologies for sources, optics, and detectors needed for at-wavelength EUV mask inspection currently exist but significant efforts to develop the numerous system components would be necessary to implement practical EUV mask inspection tools.
Recent experimental results from an actinic EUVL mask blank defect inspection system are presented. Bright-field and dark-field scans from various programmed defect samples are reported. Our results show that the current system can detect defects as small as 0.2 micrometers . Substrate roughness is identified as the limitation to the detection sensitivity. A preliminary defect counting experiment is reported and future improvements for practical defect counting are discussed.
In the last two years, we have developed tow Extreme UV (EUV) mask fabrication process flows, namely the substractive metal and the damascene process flows, utilizing silicon wafer process tools. Both types of EUV mask have been tested in a 10X reduction EUV exposure system. Dense lines less than 100 nm in width have been printed using both 0.6 micrometers thick top surface imaging resists and ultra-thin DUV resist. The EUV masks used in EUV lithography development work have been routinely made by using the current wafer process tools. The two EUV mask processes that we have developed both have some advantages and disadvantages. The simpler subtractive metal process is compatible with the current reticle defect repair methodologies. On the other hand, the more complex damascene process facilitates mask cleaning and particle inspection.
Extreme UV Lithography (EUVL) is one of the leading candidates for the next generation lithography, which will decrease critical feature size to below 100 nm within 5 years. EUVL uses 10-14 nm light as envisioned by the EUV Limited Liability Company, a consortium formed by Intel and supported by Motorola and AMD to perform R and D work at three national laboratories. Much work has already taken place, with the first prototypical cameras operational at 13.4 nm using low energy laser plasma EUV light sources to investigate issues including the source, camera, electro- mechanical and system issues, photoresists, and of course the masks. EUV lithograph masks are fundamentally different than conventional photolithographic masks as they are reflective instead of transmissive. EUV light at 13.4 nm is rapidly absorbed by most materials, thus all light transmission within the EUVL system from source to silicon wafer, including EUV reflected from the mask, is performed by multilayer mirrors in vacuum.
We report wavefront measurement of a multilayer-coated, reflective optical system at 13.4-nm wavelength performed using a novel phase-shifting point-diffraction interferometer. Successful interferometric measurements of a 10x Schwarzschild objective designed for extreme ultraviolet projection lithography with 0.1-micrometer resolution demonstrate high- precision with sub-nanometer resolution. The goal of the interferometry is to achieve wavefront measurement accuracy beyond lambda/50 rms at EUV wavelengths. Preliminary measurements are discussed and the paths toward achieving the target accuracy are identified.
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