This paper presents a feasibility study on patterning the critical layers of Bit-Line Periphery (BLP) and Storage Node Landing Pad (SNLP) for advanced 10nm node DRAM with sub-40nm pitch using a single EUV patterning. Source Mask Optimization (SMO) and aerial image-based Optical Proximity Correction (OPC) were initially conducted to classify image data and identify potential weak points of the primary patterning mask. A secondary patterning mask was then produced based on the resist model and design split using the obtained data on the primary mask to address these issues. Results obtained through PV-band and intensity analysis of each area in simulation, as well as ADI and AEI (After Etch Inspection) using photoresists with 2 kinds of different tones (PTD CAR and Spin-on MOR PR), demonstrated the feasibility of patterning BLP and SNLP with a single EUV mask. Additionally, Process Window Discovery (PWD) wafers were fabricated to analyze and review process margins and potential weak points through KLA inspection for systematic patterning defectivity. Furthermore, our experiments confirmed that the performance of EUV patterning with DRAM BLP/SNLP layer can be expected to improve by reducing the dose (in mJ/cm2) by approximately 30% using a secondary mask by retarget bias split and resist model OPC.
As the industry continues to scale DRAM cell size, EUV lithography techniques have been considered in one or multiple steps. We have explored a single mask solution to pattern the bit-line-periphery (BLP) and the storage node landing pad (SNLP). Normally, for such varied types of structures as honeycomb arrays, SWD, S/A and Core, multiple masks are required. In this paper, we have explored a single EUV mask approach. First, a freeform EUV light source (in the source mask optimization, or SMO, process) was generated targeting a 36nm pitch honeycomb array and BLP structures. Then, curvilinear optical proximity correction (OPC) was applied to the target design (as shown in Figure 1) such that the performance meets qualified process window variation bands (PVBs) with proper curvilinear mask rule check (MRC). It is important to note that only an optical model was used for SMO and OPC without a resist model in this task. For the wafer process, we have used a dark field mask and metal oxide resist (MOR) photoresist and negative tone development (NTD). This was followed by transferring the pattern into a suitable hardmask for optical defect characterization using the KLA broadband plasma (BBP) 29xx tool as shown in Figure 2. Process window characterization was done to discover a unified defect-free window for both honeycomb array and BLP structures.
The common process window of EUV patterning is being limited when the 1-dimensional (1D) pitch shrinks to 32nm or below. There are many investigations and studies that propose an alternative EUV photomask absorber to mitigate photomask 3-dimensional (3D) topology effects and can partially mitigate the contrast fading effect and reduce through pitch best focus shift.1,2,3 Another method to counter photomask 3D effects, is sub-resolution assistant features (SRAFs). SRAF insertion is one possible way to create a dense optical environment, which will prevent strong best focus shift from semi-isolated to isolated features. However, the side effect of SRAF insertion is unwanted SRAF printing occurring on the surface or bottom of the photoresist.4 In order to predict the partial removal or small residues of photoresist after the lithographic development process, a flow of compact photoresist 3D modeling (R3D) in conjunction with stochastic modeling can be adopted. In this paper, a bright field EUV photomask with regular 1D line-space grid design and positive tone development (PTD) are considered. The SEM images of through pitch 1D structures with various sizes of SRAFs are collected. To quantify SRAF printing, pixel brightness is compared to resist-opened background area, the printing SRAF regions can then be identified and clustered. Compact resist stochastic modeling is also performed by line-width roughness (LWR) sampling and used to predict SRAFs printing pixels by using Average Printing Area (APA) method with R3D modeling.5 Therefore, not only severe SRAF printing events can be predicted well, but also the accurate prediction of SRAF printing with very low probabilities can also be achieved.
Aberration is one of the contributors to edge placement error (EPE) variation and overlay error in the scanner system. In the EUV system, aberration-induced wavefront errors can have a much bigger impact than the in a DUV system due to significantly reduced wavelength and heating effect from illumination energy loss through reflective optics. Although in-situ metrology of the scanner system can extract wavefront information accurately and it can be feedbacked for aberration control, dynamic heating effects during long-time full-field exposures and tool-to-tool performance gap by aberration variation in high volume manufacturing (HVM) should be directly monitored on the wafer patterning result for reliable process control. This study aims to identify the feasibility of aberration monitoring on the wafer by using an e-beam metrology tool. Simulation work is performed first for source adjustment and the selection of generic designs of aberration-sensitive patterns of dark field Ta-based EUV masks. For quantitative analysis, the wavefront phase error is directly modulated (dialed-in) in the EUV system, and a wafer is exposed for each modulation condition. The wavefront error induced by the modulated aberration is extracted from measured CD data, using an optical simulation model. We finally discuss the correlation between the extracted aberration and the modulated wavefront error. Based on the result in this work, we investigate the feasibility of the potential application of e-beam metrology on dynamic aberration variation in HVM.
The new generation of 10nm node DRAM devices have now adopted EUV based patterning techniques. With further shrink in design rules, single exposure EUV processes will be pushed further using advanced photoresists and new mask types. However, in absence of high NA EUV lithography ready for high volume manufacturing (HVM) until at least 2025, acceptable local CD (critical dimensions) uniformity and yielding process windows at low exposure dose are a challenge for single exposure EUV. Further, for EUV implementation in sub-32nm pitch DRAM capacitator patterning applications, multi-patterning techniques must be explored. In this paper, EUV based double-patterning techniques have been demonstrated to pattern honeycomb array contact holes and pillars. The processing utilizes two EUV masks, using simple angled line space patterns. We have explored two different types of double patterning options: litho-freeze-litho-etch (LFLE) to pattern contact holes and litho-etch-lithoetch (LELE) to pattern pillars. In the absence of high NA EUV, these processing techniques are useful to pattern tight pitch (e.g., 32nm) contact holes/pillars for newer generations of DRAM devices. Another key objective of this paper is to present a set of metrology characterization methods to enable proper process optimizations.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.