This course is directed towards presenting a methodology to include layout effects on circuit analysis. DFM imposes embellishments on the layout to ensure manufacturability with acceptable yields. Traditional circuit analysis and effects of process variability are performed at the schematics level using models for process corners and may lead to excessive guardbanding. Circuit Analysis that is able to predict impact and sensitivity of layout modifications uses circuit simulators together with information derived from litho simulations and helps the designer to ascertain that the layout accompanying the design meets the manufacturability criteria.

Sub-90nm CMOS technologies are giving rise to significant variation in physical parameters of VLSI designs which has adverse impact on their electrical behavior. Most manufacturing-oriented professionals are familiar with the variations in physical parameters. This course will provide attendees with knowledge of how these physical variations impact the circuit operations, i.e., their electrical behavior. The impact on timing as well as power will be discussed. We will describe relative impact of these variations on various circuit families as well as circuit design techniques to mitigate the impact of manufacturing variations. Due to the large mangnitude of these variations, it is clear that designing for worst case behavior leaves significant performance on the table. We will discuss how systematic variation can be exploited in the current static timing methodology if it is known. A statistical timing and design methodology will also be discussed that can help regain some of this performance. With an eye towards the future, we will also explore manufacturing aware design closure. The course will be illustrated with practical examples throughout.