How to maintain the Moore’s Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.
In this paper, we report effects of indium implant and post- RTA on performance and reliability of Sub-100nm retrograde channel NMOSFETs. NMOSFETs with gate lengths down to 50nm were fabricated using resist trimming technique. Indium or boron implant was used for channel doping. Good device performance was obtained with indium implant and a post-RTA. Systematic investigation on effects of indium implant and post-RTA is performed. Indium channel implant was found to improve Vt roll-off, but worsen body effect. High leakage current of age oxide at STI edges with indium implant was observed and a post-RTA was found to be effective to improve this extrinsic gate oxide reliability. Effective mobility improvement with indium channel doping and further improvement with a post-RTA were also observed. An indium- induced oxide thinning was revealed and a post-RTA was found to enhance the thinning effect. Hot carrier stress tests show that indium doped retrograde channel improves hot carrier degradation and a post-RTA furthers this improvement.
Device degradation due to hot-carrier injection in sub-100 nm gate length devices has been investigated. 90 nm gate length (CD SEM) N-MOSFETs with 2.2 nm nitrous oxide (Idsat equals 735 uA/micrometer, Idoff equals 1.1 nA/micrometer Vdd equals 1.5 V) are electrically stressed and measured up to 200,000 seconds. Both VgIsubmax and Vg equals Vd stressing conditions at 1.8, 2.0, 2.2 V, 2.5 V and 2.8 V are performed. Contrary to traditional understanding, Vg equals Vd, i.e. channel hot carrier injection CHCI), stress causes more idlin, Idsat, Vt and Gm degradations. Similar trends are observed in NMOS devices fabricated with 1.6 nm thermal and nitrous oxides as well as 1.3 nm nitric oxides. CHCI being a worst case DC hot carrier stress condition for sub-100 nm devices with ultra- thin gate oxides is a gate-length and stress-voltage dependent phenomenon. For 90 nm NMOS devices, VgIsubmax degradation becomes dominant again when stress voltage is 2.0 V or less. For a set stress voltage, e.g. 2.5 V, VgIsubmax degradation is observed to be dominant for gate length (Leff) larger than 130 nm (90 nm). Negligible device degradation (less than 1%) under high uniform gate field tunneling stress suggests lateral electric field is causing the device degradation and CHCI as the dominant stress mechanism in sub-100 nm N-MOSFETs with direct tunneling oxides. Post-stress sub-threshold swing, charge-pumping and DC-current-voltage characterization suggest that stress-generated interface trap is a major cause of device degradation.
This paper reports experimental results of polysilicon gate patterning for sub-100 nm and deep sub-100 nm (less than 50 nm) MOS technology development. Sub-100 nm and deep sub-100 nm polysilicon gates have been achieved using an aggressive etch bias process combined with deep ultraviolet (DUV) lithography. In this paper, we report results on BARC effect, uniformity and iso/dense bias, etch selectivity, poly profile sensitivity, endcap pullback and metrology issues. We have achieved pitting free etch for ultra thin gate oxides down to 15 A. Deep sub-100 nm (approximately 50 nm) photo resist lines and deep sub-100 nm (less than 50 nm) poly gates with a good profile have been obtained.
Gate insulator/stack scaling is arguably one of the most challenging aspects of device scaling. As gate lengths are scaled into the sub-100 nm regime, alternate materials other than SiO2 will be needed to continue device scaling. The SIA roadmap has called for introduction of high-k materials below the 100 nm technology node due to problems with direct tunneling in SiO2. However, introduction of high-k poses many challenges in the process/materials side in CMOS process integration. Also, there are device scaling issues that are equally important. When k is increased beyond a certain level, unforeseen effects come to play. A phenomenon known as fringing-induced barrier lowering (FIBL) increases Ioff and degrades the subthreshold swing of the device. This paper describes this phenomenon, and provides insight into device scaling with high k materials. A host of other tradeoffs, especially those concerning control of Ioff and speed, are examined using 2-D simulator and analytical models. Suggestions to control FIBL are also detailed.
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