Dr. Gianfranco Capetti Profile

Dr. Gianfranco Capetti

Engineer at Micron Agrate

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Publications (10)

Proceedings Article | 4 March 2010 Paper

Laser bandwidth effect on overlay budget and imaging for the 45 nm and 32nm technology nodes with immersion lithography

Umberto Iessi, Michiel Kupers, Elio De Chiara, Pierluigi Rigolli, Ivan Lalovic, G. Capetti

Proceedings Volume 7640, 76402B (2010) https://doi.org/10.1117/12.846552

KEYWORDS: Laser stabilization, Optical simulations, Overlay metrology, Chromatic aberrations, Laser applications, Lithography, Metrology, Distortion, Immersion lithography, Critical dimension metrology

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Proceedings Article | 16 March 2009 Paper

High-order distortion effects induced by extreme off-axis illuminations at hyper NA lithography

Pierluigi Rigolli, Gianfranco Capetti, Elio De Chiara, Leonardo Amato, Umberto Iessi, Paolo Canestrari, Christine Llorens, Sanne Smit, Lionel Brige, Johannes Plauth

Proceedings Volume 7274, 72742T (2009) https://doi.org/10.1117/12.814148

KEYWORDS: Overlay metrology, Lithographic illumination, Distortion, Lithography, Semiconducting wafers, Device simulation, Reticles, Yield improvement, Scanners, Wavefronts

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Proceedings Article | 1 April 2008 Paper

Impact of medium and long range effects on poly gate patterning

Manuel Tagliavini, Elisabetta Annoni, Pietro Cantù, Gianfranco Capetti, Chiara Catarisano, Roberto Colombo, Giovanni Magri, Marcello Ravasio, Federica Zanderigo

Proceedings Volume 6924, 69243Y (2008) https://doi.org/10.1117/12.771968

KEYWORDS: Critical dimension metrology, Photomasks, Etching, Optical lithography, Optical proximity correction, Semiconducting wafers, Lithography, Model-based design, Reticles, Metrology

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Proceedings Article | 1 April 2008 Paper

Combined mask and illumination scheme optimization for robust contact patterning on 45nm technology node flash memory devices

Alessandro Vaglio Pret, Gianfranco Capetti, Maddalena Bollin, Gina Cotti, Danilo De Simone, Pietro Cantù, Alessandro Vaccaro, Laura Soma

Proceedings Volume 6924, 69243B (2008) https://doi.org/10.1117/12.772676

KEYWORDS: Photomasks, Fiber optic illuminators, Lithography, Semiconducting wafers, Optical lithography, Binary data, Scanning electron microscopy, Immersion lithography, Image processing, Phase shifts

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Proceedings Article | 27 March 2007 Paper

Sub-k1 = 0.25 lithography with double patterning technique for 45-nm technology node flash memory devices at λ = 193nm

Gianfranco Capetti, Pietro Cantù, Elisa Galassini, Alessandro Vaglio Pret, Catia Turco, Alessandro Vaccaro, Pierluigi Rigolli, Fabrizio D'Angelo, Gina Cotti

Proceedings Volume 6520, 65202K (2007) https://doi.org/10.1117/12.711976

KEYWORDS: Photomasks, Double patterning technology, Overlay metrology, Etching, Reticles, Lithography, Optical proximity correction, Manufacturing, Semiconducting wafers, Scanning electron microscopy

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An enormous pressure is currently put on Resolution Enhancement Techniques to meet the deadline for the development of high density memory devices. The prevailing conviction is to consider water immersion lithography as the choice for manufacturing 45nm technology node devices. Even if a huge effort to face immersion specific issues has been done (on defectivity, micro-bubbles, contamination, overlay control, hyper NA imaging, birefringence), a technology solution to image the desired features and densities must be available till now in order to anticipate all the steps involved in the process integration before the complete assessment of the immersion infrastructure. Moreover, the forecasted solutions for 32nm and 22nm technology nodes remain uncertain, strongly depending on current and near future development of high index fluids for immersion lithography and EUV availability. These temporal lacks of technology options are forcing scanner suppliers and IC manufacturers to include also double exposure in the group of viable choices for future development. Double patterning (double exposure and double etch) is surely a fascinating solution for overcoming the physical resolution limit of k₁ = 0.25 of imaging systems. Various papers in these last two years demonstrated an increasing interest in the exploration of such kind of technique to extend as much as possible ArF dry exposure tools. Though the concept of this technique is simple and well known, there are various technical issues which must be solved before moving to a real implementation in the manufacturing phase. In this paper we want to present the experimental results of the application of double patterning to the definition of a 45nm technology node Flash memory device, reaching a k₁ ~ 0.20 using 193nm dry lithography. Flash memory design introduces imaging critical points in several levels: active, contacts, and first metallization. For each of these layers, a dedicated study of double exposure has been performed in order to develop a combined litho-etch process to pattern the requested features density. Different issues will be reported, related to process choices (hard mask, resist compatibility), overlay performances, OPC and layout decomposition. Experimental process windows of dedicated test masks with lines and spaces and contact holes are shown. A deep study on overlay performance and possible optimizations has been performed and will be reported. Finally, we will demonstrate that double exposure technique can be used to anticipate process integration of critical lithography steps for high density memory devices at 45nm technology node.

Proceedings Article | 21 March 2006 Paper

Alternated phase-shift mask for 45nm node contact hole patterning

Pietro Cantu, Gianfranco Capetti, Chiara Catarisano, Fabrizio D'Angelo, Alessandro Vaccaro

Proceedings Volume 6154, 615447 (2006) https://doi.org/10.1117/12.656356

KEYWORDS: Photomasks, Phase shifts, Etching, Quartz, Manufacturing, Critical dimension metrology, Optical lithography, Resolution enhancement technologies, Lithography, Phase measurement

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Proceedings Article | 10 May 2005 Paper

Evaluation of Hitachi CAD to CD-SEM metrology package for OPC model tuning and product devices OPC verification

Pietro Cantu, Gianfranco Capetti, Chiara Catarisano, Fabrizio D'Angelo, Elena Evangelista, Ermes Severgnini, Silvia Trovati, Mauro Vasconi, Takumichi Sutani, Stephan Wahl, Robert Steffen

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.601909

KEYWORDS: Computer aided design, Scanning electron microscopy, Optical proximity correction, Semiconducting wafers, Image acquisition, Metrology, Critical dimension metrology, Instrument modeling, Detection and tracking algorithms, Visualization

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Optical proximity corrections are widely used in semiconductor industry to compensate non-linear effects occurring when printing features smaller than exposure wavelength. Most advanced OPC software packages simulate optical behavior starting from a physical description of illumination and projection optics, while the characterization of resist development and etch loading effects is still performed empirically, with different approaches that, generally, require the collection of a huge amount of experimental data. Due to the wide variety of target patterns, which makes conventional CD-SEM recipe creation impossible, critical dimension (CD) measurements are usually performed manually, requiring long time and, despite the attention paid while measuring, with poor guarantee of repeatability. The introduction of 193nm resists, much more sensitive to SEM e-beam exposure if compared to 248nm materials, required increased attention to be paid on both focusing and measuring phases in order to obtain reliable results. As well as OPC model tuning, the verification of correction effectiveness on product devices is performed almost in the same way leading to the same kind of issues. In order to overcome most of these problems ST is evaluating a new CD metrology package from Hitachi High Technologies; this tool allows fully automatic CD measurements starting from GDS II coordinate input. The exact recognition of measurement locations is obtained through an algorithm, based on the superposition of the drawn GDS II layout to the SEM wafer images, which allows achieving high positioning accuracy. The introduction of the tool significantly reduces measuring time down to the range of normal automated CD measurement times, while guarantying improved repeatability and optimized conditions even with 193nm resists due to the possibility of defining different structures for addressing and focusing before the measurement. This new system opens new perspectives in OPC modeling giving the opportunity of a more accurate model tuning, required by 65 nm technology node, and enables an extensive product devices OPC verification presently impossible due to time and procedure issues.

Proceedings Article | 28 May 2004 Paper

Customized illumination schemes for critical layers of 90-nm node dense memory devices in ArF lithography: comparison between simulation and experimental results

Gianfranco Capetti, Maddalena Bollin, Annalisa Pepe, Gina Cotti, Sara Loi, Umberto Iessi

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.533707

KEYWORDS: Diffraction, Binary data, Photomasks, Lithographic illumination, Lithography, Nanoimprint lithography, Scanners, Semiconducting wafers, Resolution enhancement technologies, Edge roughness

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Proceedings Article | 28 May 2004 Paper

Evaluation of IDEALSmile for 90-nm FLASH memory contact holes imaging with ArF scanner

Pietro Cantu, Gianfranco Capetti, Sara Loi, Marco Lupo, Annalisa Pepe, Kenji Saitoh, Kenji Yamazoe, Yasuo Hasegawa, Junji Iwasa, Olivier Toublan

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.534065

KEYWORDS: Monochromatic aberrations, Printing, Photomasks, Optical proximity correction, Scanners, Binary data, Resolution enhancement technologies, Lithography, Spherical lenses, Visualization

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Proceedings Article | 30 July 2002 Paper

Evaluation of double focal plane exposure technique for 248-nm and 193-nm lithography for semidense trenches and contacts

Francois Weisbuch, Francesco Enrichi, Gianfranco Capetti, Govanni Bianucci, Gina Cotti

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474542

KEYWORDS: Lithography, Image processing, Data modeling, Line edge roughness, Semiconducting wafers, Electroluminescence, Image resolution, 193nm lithography, Photomasks, Optical lithography

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Showing 5 of 10 publications

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