Various approaches have been utilized to extend the dynamic range of the CMOS image sensor, which are based on a
linear-logarithmic CIS, overflow integration capacitor and multiple sampling or individual pixel resetting. These
approaches, however, suffer from noise, nonlinearity, lower sensitivity, reduced operating speed and lower resolution. In
order to overcome these problems, we have previously proposed a dynamic range extension method by combining output
signals from two photodiodes with different sensitivities, such as a high-sensitivity photodiode and a low-sensitivity
photodiode. The proposed active pixel sensor has been fabricated by using 2-poly 4-metal standard CMOS process and
its characteristics have been measured. It is found that charges in the high- and low-sensitivity photodiodes could be
mixed each other and the lost image information of the high-sensitivity photodiode could be regenerated using the
charges in the low-sensitivity photodiode, as shown by simulation results. Dynamic range extension of the proposed
active pixel sensor has been experimentally verified.
A dynamic range (DR) extension technique based on a 3-transistor (3-Tr.) active pixel sensor (APS) and dual image
sampling has been proposed. The feature of the proposed APS was that the APS used two photodiodes with different
sensitivities, a high-sensitivity photodiode and a low-sensitivity photodiode. Operation of the proposed APS was
simulated by using a 128×128 pixel array. Compared with previously proposed wide DR (WDR) APS, the proposed
approach has several advantages; no-external equipments or signal processing for combining images, no-additional timerequirement
for additional charge accumulation, adjustable DR extension and no temporal disparity.
CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help
develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of
the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a
resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed
with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a
standard CMOS technology. The experimental results have been nicely matched with our prediction.
In this paper, a vision chip for a contrast-enhanced image based on a structure of a biological retina is introduced. The
key advantage of this structure is high speed of signal processing. In a conventional active pixel sensor (APS), the charge
accumulation time limits its operation speed. In order to enhance the speed, a logarithmic APS was applied to the vision
chip. By applying a MOS-type photodetector to the logarithmic APS, we could achieve sufficient output swing for the
vision chip in natural illumination condition. In addition, a CMOS buffer circuit, a common drain amplifier, is
commonly used for both raw and smoothed images by using additional switches. By using the switch-selective resistive
network, the total number of MOSFETs for a unit pixel and the fixed-pattern noise were reduced. A vision chip with a
160×120 pixel array was fabricated using a 0.35 &mgr;m double-poly four-metal CMOS technology, and its operation was
experimentally investigated.
In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate
that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 &mgr;m 2-poly 4-
metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 &mgr;m pixels. The unit pixel has a
configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer
gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer
gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 103 A/W
without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination
as low as 5 lux.
The noise problem, such as the fixed pattern noise (FPN) due to the process variation, should be considered when designing a vision chip. In this paper, we proposed an edge detection circuit based on biological retina using an offset-free column readout circuit (OFCRC) to reduce the FPN occurring in the photo-detector. The OFCRC consists of one source follower, one capacitor and five transmission gates. Thus, it is simpler than a conventional correlated double sampling (CDS) circuit. A vision chip for edge detection has been designed and fabricated using a 0.35μm 2-poly 4-metal CMOS process and its output characteristics have been investigated.
Numerical increment of analog circuits causes power consumption to increase and requires a larger chip area. In designing an analog complementary-metal-oxide-semiconductor (CMOS) vision chip for edge detection, power consumption should be considered. It restricts the number of the edge detection circuit which is based on the edge detection mechanism of vertebrate retina. In this paper, we applied electronic switches to an analog CMOS vision chip for edge detection to reduce the power consumption. Also, we propose a method to implement vision chip with higher resolution, which is to separate pixels for edge detection into a 128×128 photodetector array and a 1×128 edge detection driving circuit array. The capability to minimize power consumption was investigated by SPICE. Estimated power consumption with 128×128 pixels was below 20mW.
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