As the semiconductor industry rapidly approaches the 3nm lithography node, on product overlay (OPO) requirements have become tighter and as a result, residuals magnitude requirements have become even more challenging. Metrology performance enhancements are required to meet these demands. Color Per Layer (CPL) is a unique imaging overlay metrology approach that enables the measurement of each layer with individually-optimized wavelength and focus position. CPL allows the user to custom-define the most suitable conditions per layer, thereby ensuring optimal performance. Imaging-based overlay (IBO) utilizes CPL in order to overcome inaccuracies due to interactions between bottom and top layers. These layers are fundamentally different in that the top grating is usually the photoresist layer, but the bottom grating can be any process layer. Therefore, optimizing the conditions for each layer will maximize measurement accuracy. KLA’s Archer™ 700 metrology tool addresses these metrology challenges by putting CPL to use, where the Wave Tuner (WT) allows the user to select a specific wavelength. This paper presents this novel CPL approach and discusses its reduction in OPO and contrast, and reviews use cases from DRAM and 3D NAND. We will present the results from these case studies, focusing on SK Hynix DRAM production wafers.
Multi-patterning processes have become common in the leading-edge semiconductor industry. These processes require a good patterning uniformity over the wafer while different process steps have impact. The initial lithography steps can be nearly perfect, but the CD variation after a trim process may cause CD variation after the spacer deposition. In fact, that leads to final non-uniformity of the final CD. Monitoring and controlling the individual CD parameters is not sufficient to ensure a stable process. We define a set of new KPIs, taking all contributions into account and using macro measurement data. We show that a reliable monitoring is achieved to meet the process specifications.
For the sub-20 nm DRAM nodes, wafer-to-wafer (W2W) variation is one of the major contributors to on-product overlay (OPO). One way to reduce the W2W variation is by applying overlay corrections on wafer level on top of per lot / per chuck corrections. These overlay corrections can e.g. be based on measurements of the OPO on the wafers to be corrected prior to rework and re-exposure. Measuring OPO on every wafer is not preferred due to the resulting metrology cost increase. Hence, wafers are typically assigned to a limited amount of groups, which are in turn assigned one common correction set for all the wafers within a particular group. The common corrections are obtained from measuring wafers from the respective groups. In this paper, we present results obtained by a different approach, where the wafer grouping is deduced from metrology data that is available prior to the exposure of the lot. Aim of this approach is to balance overlay control and OPO metrology effort. We experimentally demonstrated the benefit of our approach on one of the critical layers of a sub-20 nm DRAM product of SK hynix. The experiment was executed in a rework scenario, which involves exposing and measuring OPO on selected send-ahead (SAHD) wafers, their subsequent rework, and re-exposure of the full lot using per-group corrections derived from the OPO measurements of the SAHDs. The results of this experiment indicate a promising OPO improvement. Simulations performed on additional lots and for 3 additional layers confirm the validity of our results.
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