With the inherent advantages in SOI CMOS technology, minimizing DC and switching floating body effects have enabled high speed digital processors with more than a 25% improvement over bulk silicon CMOS design. Currently, there is a need for a more comprehensive understanding of AC characteristics on SOI CMOS technology for mixed-mode baseband and RF (radio frequency) applications. The objective of this paper is to present a study of unique AC floating body effects and the resultant low-frequency noise overshoot phenomenon in SOI CMOS technology. Further study of their impact on the RF arena will also be discussed.
Two charge-scaling successive approximation A/D converters for on-focal-plane column-parallel data processing in CMOS active pixel image sensors (APS) are presented. The converters are designed in a thin but long fashion to fit a pitch size of 40 micrometers for 2.0 micrometers technology and 24 micrometers for 1.2 micrometers technology. Designed for multimedia and other commercial and industrial applications, each in column A/D converter achieves a 8 bit resolution and accuracy with a signal swing of 1 V. Maximum conversion rate exceeding 200 kHz enables high speed digital readout beyond 200 frames/sec for large format 1 K X 1 K CMOS image sensors. A prototype device of 64 X 64 APS image array with 8 bit digital output was demonstrated up to 1 kHz frame rate, and with column-wise non-uniformity less than 2 LSBs.
Results are presented of a process-development effort to achieve a 1-Mrad silicon (Si) radiation-hardening capability at temperatures down to 40 K, using Texas Instruments high volume, 1-micrometer commercial process. The one-micrometer process was characterized at 77 K and 40 K: radiation effects on the baseline SiO2 gate dielectric and N-channel field effect transistor edges were observed, as were freeze-out and hot-carrier effects of the lightly doped drain implants. These freeze-out phenomena were confirmed, using SUPREM, MINIMOS, and MEDICI. The simulated data compared favorably with measured results. Simulations were run, using various implant doses and profiles to eliminate the freeze-out and hot-carrier effects in the new process. Devices having these simulated profiles were processed, and the results are presented.
As device dimension is scaled into the deep-submicron regime, high quality thin-gate dielectric films with very uniform thickness are becoming increasingly necessary. The requirements on these thin gate oxides are--accurate control in growth, high breakdown field, low interface state density, good hot carrier reliability, good TDDB properties, and effective masking against impurity diffusion. Rapid thermal oxidation is one method to achieve high quality sub- 10 nm oxide films. In addition, by simultaneously or sequentially introducing gases other than O2;, such as NH3 or N2O, during the oxidation processes, one can dramatically improve certain aspects of the resulting dielectrics. Films with very high dielectric breakdown voltage and hot-carrier-hardness have been achieved. When the process is optimized, the performance of these transistors is also excellent. This paper will discuss the challenges facing gate dielectrics for sub-half micron MOSFET's, and the use of rapid thermal oxidation to achieve high quality gate dielectrics for these applications.
KEYWORDS: Field effect transistors, Resistance, Transistors, Silicon, Very large scale integration, Microelectronics, Manufacturing, Reliability, Ionization, Silicon films
The fully depleted silicon-on-insulator (SOI) MOSFET is a candidate for deep-submicron VLSI due to the numerous advantages over bulk silicon devices, including resistance to short- channel effects, reduced parasitic capacitances, improved subthreshold slope, and higher transconductance. However, these devices can exhibit a low source-drain breakdown voltage, which is a result of the triggering of the parasitic bipolar transistor. The breakdown voltage in fully depleted SOI MOSFET's has been studied as a function of both silicon film thickness and channel length. In the long-channel regime (> 2 micrometers ), the breakdown voltage is found to decrease as film thickness is decreased. This is attributed to increasing lateral electric fields as film thickness decreases. As channel lengths are reduced, however, the ultra-thin devices eventually exhibit higher breakdown voltages than the thicker devices. The higher breakdown voltage in the ultra-thin devices is attributed to improved resistance to punchthrough and charging effects. As the channel length is reduced, there is a transition from a bipolar-dominated breakdown regime to a punchthrough-dominated regime. The channel length at which punchthrough becomes significant is greater in thicker films, resulting in lower breakdown voltages at deep-submicron channel lengths. Therefore, ultra-thin films may be preferred over thicker SOI for deep-submicron VLSI.
Hot carrier device lifetime diminishes dramatically as operating temperature decreases. The hot carrier lifetime at liquid nitrogen temperature is usually several orders of magnitude lower than at room temperature. In this work, we show the dependence of hot carrier device lifetime of LDD nMOSFETs on temperature and stress condition in the temperature range from 78 K to room temperature. There is a cross-over point at which the worst-case hot carrier stress condition switches from Vg approximately equals 1/2 Vd (Vg Ibmax) to Vg equals Vd with decreasing temperature. Consequently, the dominant damage mechanism switches from interface state generation to trapped charge generation.
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