Mr. Jean-Christophe Le-Denmat Profile

Jean-Christophe Le-Denmat

at STMicroelectronics

SPIE Involvement:

Author

Publications (15)

Proceedings Article | 24 March 2016 Paper

Paper

Resist 3D model based OPC for 28nm metal process window enlargement

P. Fanton, J. C. Le Denmat, C. Gardiola, A. Pelletier, F. Foussadier, C. Gardin, J. Planchot, A. Szucs, O. Ndiaye, N. Martin, L. Depre, F. Robert

Proceedings Volume 9778, 97781U (2016) https://doi.org/10.1117/12.2218916

KEYWORDS: 3D modeling, Optical proximity correction, Metals, 3D metrology, Optical lithography, Evolutionary algorithms, Photomasks, Scanning electron microscopy, Critical dimension metrology, Image processing, Etching, Calibration, Artificial intelligence, Reliability

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Proceedings Article | 18 March 2015 Paper

Paper

Fast detection of manufacturing systematic design pattern failures causing device yield loss

Jean-Christophe Le Denmat, Nelly Feldman, Olivia Riewer, Emek Yesilada, Michel Vallet, Christophe Suzor, Salvatore Talluto

Proceedings Volume 9427, 942705 (2015) https://doi.org/10.1117/12.2085307

KEYWORDS: Manufacturing, Metals, Design for manufacturability, Semiconducting wafers, Optical proximity correction, Diagnostics, Photomasks, Wafer inspection, Statistical analysis, Optical lithography

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Starting from the 45nm technology node, systematic defectivity has a significant impact on device yield loss with each new technology node. The effort required to achieve patterning maturity with zero yield detractor is also significantly increasing with technology nodes. Within the manufacturing environment, new in-line wafer inspection methods have been developed to identify device systematic defects, including the process window qualification (PWQ) methodology used to characterize process robustness. Although patterning is characterized with PWQ methodology, some questions remain: How can we demonstrate that the measured process window is large enough to avoid design-based defects which will impact the device yield? Can we monitor the systematic yield loss on nominal wafers? From device test engineering point of view, systematic yield detractors are expected to be identified by Automated Test Pattern Generator (ATPG) test results diagnostics performed after electrical wafer sort (EWS). Test diagnostics can identify failed nets or cells causing systematic yield loss [1],[2]. Convergence from device failed nets and cells to failed manufacturing design pattern are usually based on assumptions that should be confirmed by an electrical failure analysis (EFA). However, many EFA investigations are required before the design pattern failures are found, and thus design pattern failure identification was costly in time and resources. With this situation, an opportunity to share knowledge exists between device test engineering and manufacturing environments to help with device yield improvement. This paper presents a new yield diagnostics flow dedicated to correlation of critical design patterns detected within manufacturing environment, with the observed device yield loss. The results obtained with this new flow on a 28nm technology device are described, with the defects of interest and the device yield impact for each design pattern. The EFA done to validate the design pattern to yield correlation are also presented, including physical cross sections. Finally, the application of this new flow for systematic design pattern yield monitoring, compared to classic inline wafer inspection methods, is discussed.

Proceedings Article | 31 March 2014 Paper

Paper

Wafer sub-layer impact in OPC/ORC models for advanced node implant layers

Jean-Christophe Le-Denmat, Jean-Christophe Michel, Elodie Sungauer, Emek Yesilada, Frederic Robert, Song Lan, Mu Feng, Lei Wang, Laurent Depre, Sanjay Kapasi

Proceedings Volume 9052, 90520D (2014) https://doi.org/10.1117/12.2047115

KEYWORDS: Semiconducting wafers, Data modeling, Optical proximity correction, Calibration, Optical lithography, Wafer-level optics, Scanning electron microscopy, Photomasks, Modulation, Lithography

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Proceedings Article | 31 March 2014 Paper

Paper

Fast integral rigorous modeling applied to wafer topography effect prediction on 2x nm bulk technologies

J.-C. Michel, J.-C. Le Denmat, A. Tishchenko, Y. Jourlin

Proceedings Volume 9052, 905223 (2014) https://doi.org/10.1117/12.2045899

KEYWORDS: Semiconducting wafers, Global system for mobile communications, Optical lithography, Photomasks, Finite-difference time-domain method, Computer simulations, Silicon, Lithography, Wafer-level optics, Optical proximity correction

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Reflection by wafer topography and underlying layers during optical lithography can cause unwanted overexposure in the resist [1]. In most cases, the use of bottom anti reflective coating limits this effect. However, this solution is not always suitable because of process complexity, cost and cycle time penalty, as for ionic implantation lithography process in 28nm bulk technology. As a consequence, computational lithography solutions are currently under development to simulate and correct wafer topographical effects [2], [3]. For ionic implantation source drain (SD) photolithography step, wafer topography influences resulting in implant pattern variation are various: active silicon areas, Poly patterns, Shallow Trench Isolation (STI) and topographical transitions between these areas. In 28nm bulk SD process step, the large number of wafer stack variations involved in implant pattern modulation implies a complex modeling of optical proximity effects. Furthermore, those topography effects are expected to increase with wafer stack complexity through technology node downscaling evolution. In this context, rigorous simulation can bring significant value for wafer topography modeling evolution in R and D process development environment. Unfortunately, classical rigorous simulation engines are rapidly run time and memory limited with pattern complexity for multiple under layer wafer topography simulation. A presentation of a fast rigorous Maxwell’s equation solving algorithm integrated into a photolithography proximity effects simulation flow is detailed in this paper. Accuracy, run time and memory consumption of this fast rigorous modeling engine is presented through the simulation of wafer topography effects during ionic implantation SD lithography step in 28nm bulk technology. Also, run time and memory consumption comparison is shown between presented fast rigorous modeling and classical rigorous RCWA method through simulation of design of interest. Finally, integration opportunity of such fast rigorous modeling method into OPC flow is discussed in this paper.

Proceedings Article | 1 October 2013 Paper

Paper

Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies

J-C. Michel, J-C. Le Denmat, E. Sungauer, F. Robert, E. Yesilada, A-M. Armeanu, J. Entradas, J. Sturtevant, T. Do, Y. Granik

Proceedings Volume 8880, 88801J (2013) https://doi.org/10.1117/12.2027291

KEYWORDS: Semiconducting wafers, Optical proximity correction, Data modeling, Silicon, Calibration, 3D modeling, Photomasks, Modulation, Scanning electron microscopy, Active optics

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Proceedings Article | 12 April 2013 Paper

Paper

Wafer topography modeling for ionic implantation mask correction dedicated to 2x nm FDSOI technologies

Jean-Christophe Michel, Jean-Christophe Le Denmat, Elodie Sungauer, Frédéric Robert, Emek Yesilada, Ana-Maria Armeanu, Jorge Entradas, John Sturtevant, Thuy Do, Yuri Granik

Proceedings Volume 8683, 86830I (2013) https://doi.org/10.1117/12.2011412

KEYWORDS: Silicon, Semiconducting wafers, Oxides, Data modeling, Calibration, 3D modeling, Scanning electron microscopy, Photomasks, Process modeling, Optical lithography

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Proceedings Article | 12 April 2013 Paper

Paper

Wafer sub-layer impact in OPC/ORC models for 2x nm node implant layers

Jean-Christophe Le-Denmat, Catherine Martinelli, Elodie Sungauer, Jean-Christophe Michel, Emek Yesilada, Frederic Robert

Proceedings Volume 8683, 868314 (2013) https://doi.org/10.1117/12.2011424

KEYWORDS: Photomasks, Semiconducting wafers, Optical proximity correction, Silicon, Optical lithography, Calibration, Lithography, Defect inspection, Inspection, Scanning electron microscopy

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Proceedings Article | 3 April 2010 Paper

Paper

Tracking of design related defects hidden by random defectivity in production environment

J. Le Denmat, V. Charbois, L. Tetar, M. Luche, G. Kerrien, F. Robert, E. Yesilada, F. Foussadier, L. Couturier, L. Karsenti, M. Geshel

Proceedings Volume 7641, 76410Y (2010) https://doi.org/10.1117/12.848763

KEYWORDS: Semiconducting wafers, Inspection, Wafer inspection, Optical alignment, Defect inspection, Finite element methods, Statistical analysis, Optical proximity correction, Etching, Control systems

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Proceedings Article | 16 March 2009 Paper

Paper

Impact of modelisation pixel size on OPC consistency

Franck Foussadier, Emek Yesilada, Jean-Christophe Le Denmat, Yorick Trouiller, Vincent Farys, Frédéric Robert, Gurwan Kerrien, Christian Gardin, Loic Perraud, Florent Vautrin, Alexandre Villaret, Catherine Martinelli, Jonathan Planchot, Jean Luc Di-Maria, Mazen Saied, Mame Kouna Top

Proceedings Volume 7274, 727416 (2009) https://doi.org/10.1117/12.814047

KEYWORDS: Optical proximity correction, Critical dimension metrology, Computer simulations, Optical simulations, Optical lithography, Current controlled current source, Optical imaging, Databases, Process modeling, Photomasks

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Proceedings Article | 19 May 2008 Paper

Paper

Model-based mask verification on critical 45nm logic masks

F. Sundermann, F. Foussadier, T. Takigawa, J. Wiley, A. Vacca, L. Depre, G. Chen, S. Bai, J.-S. Wang, R. Howell, V. Arnoux, K. Hayano, S. Narukawa, S. Kawashima, H. Mohri, N. Hayashi, H. Miyashita, Y. Trouiller, F. Robert, F. Vautrin, G. Kerrien, J. Planchot, C. Martinelli, J. L. Di-Maria, V. Farys, B. Vandewalle, L. Perraud, J. C. Le Denmat, A. Villaret, C. Gardin, E. Yesilada, M. Saied

Proceedings Volume 7028, 70280U (2008) https://doi.org/10.1117/12.793037

KEYWORDS: Photomasks, Semiconducting wafers, Bridges, Scanning electron microscopy, Critical dimension metrology, Process modeling, Optical proximity correction, Reticles, Model-based design, Logic

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Proceedings Article | 2 May 2008 Paper

Paper

New alignment marks for improved measurement maturity

U. Weidenmueller, H. Alves, B. Schnabel, B. Icard, L. Pain, J.-C. Le Denmat, S. Manakli, J. Pradelles

Proceedings Volume 6792, 679211 (2008) https://doi.org/10.1117/12.798788

KEYWORDS: Optical alignment, Semiconducting wafers, Optical lithography, Electron beams, Electron beam direct write lithography, Lithography, Signal to noise ratio, Overlay metrology, Signal detection, Wafer testing

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Proceedings Article | 28 March 2008 Paper

Paper

High throughput maskless lithography: low voltage versus high voltage

S. W. H. Steenbrink, B. Kampherbeek, M. Wieland, J. Chen, S. Chang, M. Pas, J. Kretz, C. Hohle, D. van Steenwinckel, S. Manakli, J. Le-Denmat, L. Pain

Proceedings Volume 6921, 69211T (2008) https://doi.org/10.1117/12.771971

KEYWORDS: Semiconducting wafers, Scattering, Silicon, Critical dimension metrology, Electron beam lithography, Laser scattering, Lenses, Lithography, Modulation transfer functions, Maskless lithography

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Proceedings Article | 12 March 2008 Paper

Paper

Study of SRAF placement for contact at 45 nm and 32 nm node

V. Farys, F. Robert, C. Martinelli, Y. Trouiller, F. Sundermann, C. Gardin, J. Planchot, G. Kerrien, F. Vautrin, M. Saied, E. Yesilada, F. Foussadier, A. Villaret, L. Perraud, B. Vandewalle, J. C. Le Denmat, M. K. Top

Proceedings Volume 6924, 69242Z (2008) https://doi.org/10.1117/12.774091

KEYWORDS: SRAF, Optical proximity correction, Lithography, Eye, Photomasks, Immersion lithography, Manufacturing, Logic, Switching, Printing

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SPIE Journal Paper | 1 July 2007

Complementary dose and geometrical solutions for electron beam direct write lithography proximity effects correction: application for sub-45-nm node product manufacturing

Serdar Manakli, C. Soonekindt, Laurent Pain, J. Le Denmat, Jerome Todeschini, B. Icard, B. Minghetti

JM3, Vol. 6, Issue 03, 033001, (July 2007) https://doi.org/10.1117/12.10.1117/1.2770472

KEYWORDS: Modulation, Critical dimension metrology, Electron beam direct write lithography, Point spread functions, Electron beam lithography, Cadmium sulfide, Electron beams, Optical lithography, Manufacturing, Backscatter

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Proceedings Article | 3 May 2007 Paper

Paper

Electron beam lithography simulation based on a single convolution approach: application for sub-45nm nodes

J. Le denmat, S. Manakli, B. Icard, C. Soonekindt, B. Minghetti, O. Le borgne, L. Pain

Proceedings Volume 6533, 653319 (2007) https://doi.org/10.1117/12.736519

KEYWORDS: Monte Carlo methods, Point spread functions, Electron beam direct write lithography, Optical simulations, Electron beam lithography, Electron beams, Convolution, Scattering, Photoresist processing, Laser scattering

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Showing 5 of 15 publications

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