For 28 nm technology node and below resist profiles need to be taken in to consideration during optical proximity correction (OPC) and verification. The low k1 results in a shallower depth of focus and thus thinner resists, which combined with the process limits increases the risk of resist degradation. Only considering the resist critical dimensions at a single focal plane (such as at the bottom of the resist stack) will miss the impact of the resist 3D profile, like top loss or bottom footing, which can transfer to etch hard pattern failures. To date, modeling to study resist 3D profiles has been available using rigorous simulators and has been used as a verification method for hot spots captured during full chip OPC verification, but not for full chip verification due to the high computational run time cost. This paper demonstrates a 3D resist compact OPC model concept and implementation in a full chip OPC and verification flow. The results show significant improvement for full chip OPC quality with a good correlation between simulation and real wafer hot spots. Because resist profiles are not directly correlated to etch failure, the relationship between the resist profile and etch failures and how to characterize the threshold to dispose the hot spots for the 3D compact model was also investigated.
Sophisticated designs of the pupil illumination fill of scanners and steppers permit considerable improvements of the resolution and the quality of the optical projection for certain critical patterns. However, the mask layout can have quite different requirements for the resolution as well as the shape of the critical patterns in the two spatial directions. For instance, typical DRAM designs have one orientation with much higher requirements than the other orientation.
This asymmetry can be accounted for with a corresponding pupil fill that has a reduced symmetry as well. It is for example possible to combine high resolution and high contrast of the most critical pattern in one spatial orientation at the cost of the other orientation. Unfortunately, this leads to an asymmetric source distribution with x-y dependent optical proximity effects. Therefore the transfer of one and the same pattern from the mask to the wafer will differ if this pattern is rotated by 90 degrees. But fortunately, this anisotropic mapping can be compensated by applying an appropriate optical proximity correction (OPC) which is anisotropic as well. In the current work, we measure on silicon the orientation dependent proximity effect for a customized and strongly asymmetric pupil illumination fill design. With this input data, we build a lithography simulation model which is able to reproduce this anisotropy well. We further perform full chip anisotropic OPC and present the actual success of this resolution enhancement technique with various measurement results and printed wafer images. We also discuss the challenges and problems of this method.
Sub-Resolution Assists Features (SRAF) is a well known and well described method for process window improvement. The introduction of such a technique is not always an easy task for two reasons. On one hand the SRAF placement rules must be defined very well and on the other hand an empirical resist model must be created, which describes the process. Model based Optical and Process effects correction (MB-OPC) is using an empirical model so called black box, which must be able to predict properly the printing feature for any kind of complex design configuration. When SRAF are implemented in the design, the degree of freedom for the MB-OPC can be reduced. Beside that effort to predetermine as required as possible the target layer, SRAF placement rules and SRAF printing restrictions will limit the OPC. MB-OPC has to cover both the parameters space corresponding to areas in which SRAF are placed and the parameter space for which no SRAF has been implemented. Of course, it could also be possible to apply the correction of the proximity effect of a complex design with SRAF by an extensive rule-based OPC. Nevertheless the advantage of MB-OPC exists in the possibility to verify the design after Data Preparation by simulating it with the help of the calibrated model. However one should not trust the simulation alone, always a verification of the design on silicon would be necessary, by comparing simulation to SEM images. Beside the advantages of MB-OPC also weaknesses exist in the meantime, which could require a combination of rule-based and model-based OPC, so called “hybrid OPC”. Empirical models are very often only able to predict the proximity behavior due to a certain range, which is called the optical range of a model. Distances bigger than this range will be covered by extrapolations. This procedure would be correct, if the proximity behavior was as constant as in the area inside the optical range. We generated an empirical model with the Calibre Workbench from Mentor Graphics. For the model calibration we chose structures with SRAF placement rules, which we applied to the design as well as SRAF placement rules which were not applied to the design. Afterwards, we performed simulations of critical lines over pitch including SRAF. Beside the MB-OPC, we will also describe in this paper the process steps how to generate the SRAF placement rules. The restrictions resulting from the SRAF rules are presented. Subsequently, the experimental results will show that both for symmetrical and asymmetrical structures an improvement of the process window has been obtained. Also weaknesses become clear, which place either the model or the SRAF rule-set questionable. Finally two solutions will be compared, a pure MB-OPC including the isolated lines outside of the optical range and a combination of MB-OPC with a rule-based OPC table for the isolated lines.
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