A typical new IC design has millions of layout configurations, not seen on previous product or test chip designs.
Knowing the disposition of each and every configuration, problematic or not, is the key to optimizing design for yield. In
this paper, we present a method to systematically characterize the configuration coverage of any layout. Coverage can be
compared between designs, and configurations for which there is a lack of coverage can also be computed. When
combined with simulation, metrology, and defect data for some configurations, graph search and machine learning
algorithms can be applied to optimize designs for manufacturing yield.
KEYWORDS: Manufacturing, Metals, Design for manufacturing, Raster graphics, Image classification, Data modeling, Statistical analysis, Design for manufacturability, Current controlled current source, Optimization (mathematics)
During the yield ramp of semi-conductor manufacturing, data is gathered on specific design-related process window limiters, or yield detractors, through a combination of test structures, failure analysis, and model-based printability simulations. Case-by-case, this data is translated into design for manufacturability (DFM) checks to restrict design usage of problematic constructs. This case-by-case approach is inherently reactive: DFM solutions are created in response to known manufacturing marginalities as they are identified. In this paper, we propose an alternative, yet complementary approach. Using design-only topological pattern analysis, all possible layout constructs of a particular type appearing in a design are categorized. For example, all possible ways via forms a connection with the metal above it may be categorized. The frequency of occurrence of each category indicates the importance of that category for yield. Categories may be split into sub-categories to align to specific manufacturing defect mechanisms. Frequency of categories can be compared from product to product, and unexpectedly high frequencies can be highlighted for further monitoring. Each category can be weighted for yield impact, once manufacturing data is available. This methodology is demonstrated on representative layout designs from the 28 nm node. We fully analyze all possible categories and sub-categories of via enclosure such that 100% of all vias are covered. The frequency of specific categories is compared across multiple designs. The 10 most frequent via enclosure categories cover ≥90% of all the vias in all designs. KL divergence is used to compare the frequency distribution of categories between products. Outlier categories with unexpected high frequency are found in some designs, indicating the need to monitor such categories for potential impact on yield.
The most decent scanning electron microscopy (SEM) can provide image magnification up to 500kX which seems to be suitable to image semiconductor devices for the advanced technology nodes. However, SEM images at such a high magnification often suffer from the drift and space related displacement errors, potentially causing image blur and distortion. To circumvent this, we apply the super-resolution (SR) technique to enhance the resolution of the CD-SEM metrology by using the advanced signal processing algorithms. The resolution enhancement can be realized by exploiting the multiple low resolution (LR) images that include unique information of an imaging target by looking at a slightly different position. We experimentally demonstrate image quality improvement gained by the SR technique after correcting the time-dependent drift/displacement and mapping estimated information onto the high resolution (HR) pixel grid with the non-linear pixel interpolation scheme. In addition, estimating the time-dependent drifts of the wafer position could be useful to investigate the drift properties of the CD-SEM tool.
In this paper, we demonstrate the unique advantage of dual-frequency mid-gap capacitively coupled plasma
(m-CCP) in advanced node patterning process with regard to etch rate / depth uniformity and critical dimension
(CD) control in conjunction with wider process window for aspect ratio dependent & microloading effects. Unlike
the non-planar plasma sources, the simple design of the mid-gap CCPs enables both metal and non-metal hard-mask
based patterning, which provides essential flexibility for conventional and DSA patterning. We present data on both,
the conventional multi patterning as well as DSA patterning for trenches / fins and holes. Rigorous CD control and
CDU is shown to be crucial for multi patterning as they lead to undesirable odd-even delta and pitch walking. For
DSA patterning, co-optimized Ne / Vdc of the dual frequency CCPs would be demonstrated to be advantageous for higher organic-to-organic selectivity during co-polymer etching.
Further enhancements to Monte Carlo and Self-Consistent Field Theory Directed Self-Assembly (DSA) simulation capabilities implemented in GLOBALFOUNDRIES are presented and discussed, along with the results of their applications. We present the simulation studies of DSA in graphoepitaxy confinement wells, where the DSA process parameters are varied in order to determine the optimal set of parameters resulting in a robust and etch transferrable phase morphology. A novel concept of DSA-aware assist features for the optical lithography process is presented and demonstrated in simulations. The results of the DSA simulations and studies for the DSA process using a blend of homopolymers and diblock copolymers are also presented and compared with the simulated diblock copolymer systems.
Implementation of Directed Self-Assembly (DSA) as a viable lithographic technology for high volume manufacturing
will require significant efforts to co-optimize the DSA process options and constraints with existing work flows. These
work flows include established etch stacks, integration schemes, and design layout principles. The two foremost
patterning schemes for DSA, chemoepitaxy and graphoepitaxy, each have their own advantages and disadvantages.
Chemoepitaxy is well suited for regular repeating patterns, but has challenges when non-periodic design elements are
required. As the line-space polystyrene-block-polymethylmethacrylate chemoepitaxy DSA processes mature,
considerable progress has been made on reducing the density of topological (dislocation and disclination) defects but
little is known about the existence of 3D buried defects and their subsequent pattern transfer to underlayers. In this
paper, we highlight the emergence of a specific type of buried bridging defect within our two 28 nm pitch DSA flows
and summarize our efforts to characterize and eliminate the buried defects using process, materials, and plasma-etch
optimization. We also discuss how the optimization and removal of the buried defects impacts both the process window
and pitch multiplication, facilitates measurement of the pattern roughness rectification, and demonstrate hard-mask open
within a back-end-of-line integration flow. Finally, since graphoepitaxy has intrinsic benefits in terms of design
flexibility when compared to chemoepitaxy, we highlight our initial investigations on implementing high-chi block
copolymer patterning using multiple graphoepitaxy flows to realize sub-20 nm pitch line-space patterns and discuss the
benefits of using high-chi block copolymers for roughness reduction.
Directed Self-Assembly (DSA), as an extension of current state-of-the-art photolithography, has demonstrated the
capability for patterning with resolution and cost effectiveness beyond the capability of other techniques. Previous
studies of DSA have reported encouraging benchmarks in defect density and throughput capability for the patterning
step, and such results provide a foundation for our ongoing efforts to integrate the DSA patterning step into a robust
process for fabricating device layers. Here we provide a status report on the integration of two chemoepitaxy DSA
patterning methods for the fabrication of 28nm pitch Si fin arrays. In addition to the requirements for a robust pattern
transfer process, it is also important to understand the pattern design limitations that are associated with DSA. We
discuss some of the challenges and opportunities associated with developing efficient device designs that take advantage of the capabilities of DSA.
Properly designed geometries of directing pre-patterns broaden the set of lattice symmetries and the local arrangements
of patterns achievable by directed self-assembly (DSA) of block copolymers (BCP), compared to the ones achievable in
un-directed, bulk systems.
We present the results of parametric computational simulation studies, concentrating on exploring the chemoepitaxy or
graphoepitaxy directing geometries yielding the DSA structures needed for typical integrated circuits, but not achievable
in bulk, undirected annealing of BCP. The examples include the parametric studies of chemoepitaxy and graphoepitaxy
DSA patterns etch-transferrable, respectively, into isolated lines and contact hole arrays. The results of the DSA defect
simulations are also presented and discussed.
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