Non-planar transistor architectures, such as tri-gates or "FinFETs", have evolved into important solutions to the severe
challenges emerging in thermal and power efficiency requirements at the sub-32 nm technology nodes. These
architectures strain traditional dimensional metrology solutions due to their complex topology, small dimensions, and
number of materials. In this study, measurements of the average dielectric layer thickness are reported for a series of
structures that mimic non-planar architectures. The structures are line/space patterns (≈ 20 nm linewidth) with a
conformal layer of sub-15 nm thick high-k dielectric. Dimensions are measured using a transmission X-ray scattering
technique, critical dimension small angle X-ray scattering (CD-SAXS). Our test results indicate that CD-SAXS can
provide high precision dimensional data on average CD, pitch, and high-k dielectric layer thickness. CD-SAXS results
are compared with analogous data from both top-down scanning electron microscopy and cross-sectional transmission
electron microscopy. In addition, we demonstrate the capability of CD-SAXS to quantify a periodic deviation in pitch
induced by an imperfection in the phase shift mask.
Aggressive CMOS transistor scaling requirements have motivated the IC industry to look beyond simply reducing the
film thickness or implementing different gate stack materials towards fundamentally redesigning the transistor
architecture by forcing the silicon channel to protrude upwards from the planar (2D) substrate. These 3D transistors,
namely FinFETs, ideally offer at least a 2X improvement in the drive current since more than one surface is available,
for which the minority carrier population can be adjusted by an applied voltage. However, the ability to modulate this
voltage is known to suffer due to the non-uniform film deposition on the three sides of the Si Fin. This concern is of
immediate interest because it impedes device performance and future integration since subtle differences among the
thicknesses on each side of the Fin will negatively impact threshold voltage and the capability to tune the effective work
function. It is therefore necessary to have an in-line metrology capability that can properly characterize and understand
the deposition of both the high-k and metal gate film on the sidewalls of the Fin in order for FinFETs to ultimately
replace planar CMOS devices. We will report on the ability of scatterometry to accurately measure the high-k and
metal film thickness on the sidewall of the FinFET. The results will be discussed in detail with emphasis on sensitivity
towards fin critical dimension (CD) and sidewall thickness, and comparison of the conclusions reached from the
analysis with cross-sectional transmission electron microscopy (TEM) data.
Integrated circuits have already entered the world of nanoelectronics. According to the International Technology Roadmap for Semiconductors, the industry will be extending CMOS technology through new materials and device structures for at least the next fifteen years. During that time, the gate length of nanotransistors will shrink to less than 10 nm. The electrical properties of nano-transistors will move into regime of short channel devices where new physics will result in changes in transistor operation. The number of transistors in a single IC is already approaching a number that results 2 billion functions per IC by 2010. Nano-sized features and high density will challenge metrology and characterization and most certainly move measurement further into the world of nanotechnology. Beyond CMOS, new nano-technology based devices are being considered as a means of continuing the rapid pace of technological innovation in electronics.
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