In multi patterning processes, overlay is now entangled with CD including OPC and stochastics. This combined effect is a serious challenge for continued shrink and is driving down the allowed overlay margin to an unprecedented level. We need to do everything to improve overlay where accurate measurement and control of wafer deformation is extremely important. This requires accuracy in overlay metrology that decouples target asymmetry from wafer deformation. Multiwavelength diffraction-based overlay (DBO) is positioned for providing such accuracy while maintaining the required measurement speed. At the same time, with the increase of process complexity in advanced nodes, several new types of target asymmetries are introduced. Some of such asymmetries vary even within the target / grating area (intra-grating) and some are so severe that it impacts the center of gravity shift of the overlay target.
In leading edge patterning processes, overlay is now entangled with CD including OPC residuals and stochastics. This combined effect is a serious challenge for continued shrink and can be characterized with an Edge Placement Error (EPE) budget containing multi-domain components: global and local CD, local placement errors, overlay errors, etch biases and OPC. EPE defines process capability and ultimately relates to device yield. Understanding the EPE budget leads to efficient ways to monitor process capability and optimize it using EPE based process control applications. We examine a critical EPE use case on a leading edge DRAM node. We start by constructing and verifying the EPE Budget via densely sampled on-product in-device local, global CD and Overlay metrology after the etch process step. EPE budget contributors are ranked according to their impact to overall EPE performance and later with simulated EPE performance improvements per component. A cost/benefit analysis is shown to help choose the most HVM-friendly solutions.
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