As pattern design rule of device shrinks, CD control becomes more critical and important especially for resistance devices. As CD (Critical Dimension) increases, CDU (Critical Dimension Uniformity) becomes worse generally. The question with this relationship is a starting point of our study. Mainly we focused on two points. One is which factor affects CDU. The other is whether CDU degradation with large CD happens at all cases or not. We have analyzed with simulation and experiment results about CDU with splitted mask layout CD under limited conditions such as same equipment, illumination and exposure dose. As a result, we will show the relationship between CD size and CDU.
As feature size shrinks, better critical dimension uniformity (CDU) is highly demanded in aspects of device characteristics. Intra field CDU is one of main contributor in total CD variation budget. Especially systematic CD distribution in shot, bank and MAT boundary should be strongly considered to minimize repeated error to guarantee high yield even though it is not prominent in overall CDU value.
In this paper, we investigated the several factors to affect systematic CD distribution error on intra field. First of all, localized mask CD variation caused by electron-beam scattering over local region, development loading and etch loading effect directly printed in wafer. Appropriate mask fabrication suppress CD variation at boundary region. Secondly, chemical flare effect is expected to make CD gradient at boundary region. Photo acid concentration change by sub-resolution assist feature (SRAF) can reduce the CD gradient. We demonstrated SRAF size dependency in positive tone develop (PTD) and negative tone develop (NTD) case. Thirdly, out-of-field stray light (OOFSL) due to adjacent exposed field causes CD gradient at field boundary. Exposure dose reduction is expected as a solution in this case. Even though we perfectly control CDU at boundary region after mask patterning, other process issues such as etch and CMP loading effect also make worse the CD distribution at boundary region.
Through the consideration of above factors, we optimized systematic CD distribution error at boundary region before etch. Furthermore we compared several techniques to compensate post-etch systematic CD distribution.
Woo-Yung Jung, Guee-Hwang Sim, Sang-Min Kim, Choi-Dong Kim, Sung-Min Jeon, Keunjun Kim, Sang-Wook Park, Byung-Seok Lee, Sung-Ki Park, Hoon-Hee Cho, Ji-Soo Kim
KEYWORDS: Silicon, Etching, Carbon, Polymers, Optical lithography, Silicon carbide, Coating, Line width roughness, Double patterning technology, System on a chip
The spacer patterning technique (SPT) is well known as one of the methods expanding the resolution limit and mainly
useful for patterning line & space of memory device. Although contact array could be achieved by both spacer patterning
technique and double exposure & etch technique (DEET) 1, the former would be preferable to the latter by the issues of
overlay burden and resolution limit of isolated contact. The process procedure for contact array is similar to that for line
& space which involves the 1st mask exposure, etch, carbon polymer deposition, the 2nd mask exposure and etch step
sequentially. With SPT, it would be possible to realize contact array of 30nm half pitch including 30nm isolated contact
as well as line & space of 30nm half pitch.
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