In this paper we will present initial results for logic and memory features imaged with the TWINSCAN EXE:5000 at the ASML-imec high NA lab after successful etch pattern transfer. For logic applications random logic metal designs (consisting of tight pitches and aggressive tip-to-tips) and corresponding via structures have been characterized for A14 and A10 nodes. As well, bidirectional designs enabled by high NA will be described. For memory applications, results from BLP/SNLP layer for D1d and D0a nodes will be presented.
The 10 nm technology class DRAM devices have already advanced with different patterning schemes using EUV [1-3]. Such efforts rely heavily on the choice of the underlayers, resist and the source-mask optimized (SMO) illumination mode. In this work, these concepts were explored in a single mask solution to pattern 42 nm pitch, Local Interconnect and periphery landing pad (LILP). To provide a more industry relevant solution, the use of Chemically Amplified Resists(CARs) has been adopted to pattern pillars and line/space (LS) patterns simultaneously. In addition, the following parameters have been evaluated to achieve the best printability of the two types of structures: (i) CARs tailored for high and low dose process (CAR-A and CAR-B), (ii) different underlayers (UL0, UL1, UL2), (iii) post exposure bake (PEB) conditions to determine the effect of dose-to-size and impact on the local CD uniformity (LCDU) in pillars and line width roughness (LWR) for LS. The performance comparison of different process options was done based on roughness/LCDU and dose-to-size (D-t-s).
This paper is organized as follows:
1. Experimental Method- Different combination of underlayers and resist screening using a single EUV source and mask. Optimization of the mask CDs and the overlapping process performance of pillars and LS based on the metrology inspection.
2. Underlayer performance- Choice of the underlayer based on printability performance and roughness/LCDU for a fixed resist coated on different underlayers.
3. Resist performance- Defect-free process window (PW) evaluation with different CAR coated on the best performing underlayer.
The integration of curvilinear shapes in semiconductor technology is explored. Curvilinear shapes are classified into forms using Manhattan, rectilinear, and curvilinear representations. The primary objectives of employing curvilinear shapes in Optical Proximity Correction (OPC) and mask technology are identified as error reduction and the effective representation of complex shapes. Leveraging the path optimization characteristic inherent in curvilinear shapes, their utilization was studied for semiconductor layout design. Standard cell design serves as a demonstrative example to highlight these benefits. Using the DTCO Power-Performance-Area-Cost (PPAC) assessment metric, enhancements in both electrical performance and cost efficiency are showcased, compared with designs using Manhattan shapes. We propose a step-by-step adoption strategy of curvilinear design, ranging from restrictive to partial use, and even free-form routing. In addition, we address concerns regarding data volume, outlining how curvilinear representation can effectively mitigate such issues, in OPC, mask technology and layout designs.
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