Novel mask absorber materials have been explored to improve EUV imaging performance which includes a variation of film thickness, refraction index n and the extinction coefficient k. A few promising mask absorber candidates were fabricated and evaluated using imec patterning on random logic via design with minimum pitch of 36nm. This study compares the lithography performance of low-n EUV masks with different reflectivity to our Ta-based EUV mask reference. The masks are designed with resolution enhancement techniques (RET) including source-mask optimization (SMO), optical proximity correction (OPC) and sub-resolution assist feature (SRAF) to achieve optimum mask to imaging performance. This work discusses the random logic via patterning benefits and limitations using different low-n EUV masks, along with the potential to extend the resolution of NA0.33 EUV lithography to random logic via designs down to 32nm pitch.
The requirement of larger common overlap process window in EUV patterning is getting stronger when the design pitch continues to shrink. The reflective optics in EUV generate various imaging issues due to mask 3-dimensional (M3D) effects. Therefore, sub-resolution assistant features (SRAFs) insertion is preferred for the resolution enhancement technology. SRAFs insertion can create a dense optical environment that will prevent strong best focus shift between semi-isolated and isolated features. From the previous study, SRAFs insertion and stochastic printing can be modeled and verified with a flow utilizing a compact resist 3D model (R3D) in conjunction with stochastic model. In this work, additional SRAFs investigations and studies extend to a better choice of alternative EUV mask absorbers that can mitigate M3D effects and have better lithography performance. In this paper, a low-n dark field EUV mask with regular hole grid design and positive tone development (PTD) is considered. The SEM (scanning electron microscope) images of through pitches with various SRAFs sizes and combination of SRAF to main space are collected. The SRAFs printing pixels can be captured and modeled with compact resist stochastic modeling. The results can be verified using average printed area (APA) metric with a R3D model and the simulation studies have proved the SRAFs printing sensitivity to the photomask biases.
By adopting the new design of the optics within the scanner, high-NA (0.55NA) EUV lithography enables higher resolution, which will push the EUV single patterning down to pitch 16nm (k1=0.34, the same k1 value as pitch 28nm for 0.33NA EUV single patterning). Therefore, 0.55NA EUVL is projected to print the most critical features of 2nm node (and beyond) logic chips with less patterning steps than 0.33NA EUVL, and is highly expected by the industry. Besides, novel low-n low-k absorber attenuated phase shift masks (low-n attPSMs) are commercially available recently, which have shown substantial imaging, as well as patterning performance improvements both in simulations and experiments. Thus, in this paper, we evaluate the feasibility and limits of logic metal scaling with 0.55NA EUV single pattering using source mask optimization tool, both binary and low-n attPSMs are used to pattern an imec N3 (pitch 28nm, foundry N2 equivalent) random logic metal design and the linear scaled versions (down to pitch 18nm). The impact of design orientations (horizontal vs. vertical) and mask tones (dark field vs. bright field) on patterning fidelity and overall process window is evaluated.
Imec logic N2+ design rule defines a minimum via pitch of 36nm. An EUV single patterning solution at 0.33 NA is explored on a random logic via design. From an earlier simulation study , it was shown that Ta-based bright field mask delivers the best resolution enhancement technology (RET) solution. In this paper the simulation results will be validated on wafer. Negative-tone development (NTD) with a metal-oxide resist process using a bright field (BF) mask and positivetone development (PTD) with a chemically amplified resist process using a dark field (DF) mask are compared. In addition, source-mask optimizations (SMO) including sub-resolution assist features (SRAF) were used as a RET, and optical proximity correction (OPC) was carried out on the design clips to achieve optimum lithography performance. We report the best choice among the listed options, and present our recommendation on OPC, RET and process based on the simulation and wafer data in order to improve the resolution, therefore extending the single exposure pitch limit.
Extending 0.33 NA extreme ultraviolet single patterning to 28-nm pitch becomes challenging in stochastic defectivity, which demands high-contrast lithographic images. The low-n attenuated phase-shift mask (attPSM) can provide superior solutions for individual pitches by mitigating mask three-dimensional effects. The simulation and experiment results have shown substantial imaging improvements: higher depth of focus at similar normalized image log slope and smaller telecentricity error values than the best binary mask configuration. In this work, the exploration of low-n attPSM patterning opportunity for pitch 28-nm metal design is investigated. Using generic building block features, the lithographic performance of the low-n attPSM is compared with the standard binary Ta-based absorber mask. In addition, the impact of mask tone (bright field (BF) versus dark field) on the pattern fidelity and process window is evaluated both by simulations and experiments. The results indicate that BF low-n attPSM provides the best patterning performance. Consequently, the BF low-n attPSM patterning performance is assessed with an actual imec N3 pitch 28-nm random logic metal design. The wafer data indicate BF low-n attPSM enables good patterning fidelity, as well as good overall process window with high exposure latitude (∼20 % ).
This conference presentation was prepared for Photomask Japan 2022: XXVIII Symposium on Photomask and Next-Generation Lithography Mask Technology, 2022.
Extending 0.33NA EUV single patterning to 28nm pitch becomes very challenging in terms of stochastic defectivity, which demands high contrast lithographic images. The low-n attenuated phase-shift mask (attPSM) can provide superior solutions for individual pitches by mitigating mask three-dimensional effects. The simulation and experiment results have shown substantial imaging improvements: higher depth of focus at similar normalized image log slope and smaller telecentricity error values than the best binary mask configuration. In this paper, the exploration of low-n attPSM patterning opportunity for pitch 28nm metal design is investigated. The lithographic performance of the low-n attPSM is compared to the standard binary Ta-based absorber mask. As well, the impact of mask tonality (bright-field vs. dark-field) on the pattern fidelity and process window is evaluated both by simulations and experiments.
Imec N3 logic design rules define a minimum via pitch of 36nm for a double patterning process. Enabling this pitch is crucial in terms of process time and number of masks involved. One method for extending 0.33 NA EUV is using advanced mask materials. Studies have shown that a low-n attenuated phase-shift mask (PSM) can improve EUV imaging performance, reduce mask 3D effects and improve optical contrast compared to the reference Ta-based mask. [1-3] In this paper, the impact of mask stack - Ta-based (binary or BIM) and low-n (PSM) - and mask tone - dark field (DF) vs. bright field (BF) - on a random logic Via layer will be evaluated. To pattern contact holes, we use negative tone development (NTD) metal-oxide resist process using the BF mask and positive tone development (PTD) chemically amplified resist process using the DF mask. Source mask optimization (SMO) was performed with and without subresolution assist feature (SRAF) as a resolution enhancement technology (RET). Optical proximity correction (OPC) was carried out on design clips using respective sources and mask rules at different mask tone. We show the optimum choice for this layer and present our recommendation based on current OPC simulations as well as some preliminary wafer data.
Extending 0.33NA extreme ultraviolet (EUV) single patterning to pitch 28 nm will enable significantly shorter process flow for N2 node and cost-efficiency of metal layers patterning. At the same time, EUV single patterning becomes very challenging in terms of stochastic defectivity and process window. To enable EUV single patterning at pitch 28 nm with good process window and patterning fidelity (low defectivity and line edge roughness), three mask candidates are considered: a standard binary Ta-based absorber mask, a high extinction (high-k) absorber mask, and a low-n attenuated phase-shift mask (attPSM). The patterning performance of these three mask candidates is compared by means of source mask optimization. The patterning performance of the candidate masks is assessed using an imec N3 (foundry N2 equivalent) random logic M1 layout. The impact of mask tonality (bright field versus dark field) and insertion of sub-resolution assist features (SRAFs) on pattern fidelity and process window is evaluated. Considering all the aspects, simulations indicate that the low-n attPSM has the best patterning performance both for dark-field mask with SRAFs and bright-field mask without SRAFs.
Extending 0.33NA EUV single patterning to pitch 28nm will enable metal layers cost-efficiency and significantly shorter process flow for N2 node. At the same time, EUV single patterning becomes very challenging in terms of stochastic defectivity and process window. In this paper, the lithographic performance of the M1 layer of an imec N3 (foundry N2 equivalent) random logic layout is evaluated by means of source mask optimization on these three mask candidates: a standard binary Ta-based absorber mask, a high extinction (high-k) absorber mask and a low-n attenuated phase-shift mask. The impact of mask tonality (bright field vs. dark field) and insertion of sub-resolution assist features on pattern fidelity and process window is evaluated.
EUV single patterning opportunity for pitch 28nm metal design is explored. Bright field mask combined with a negative tone develop process is used to improve pattern fidelity and overall process window. imec N3 (Foundry N2 equivalent) logic PNR (place and route) designs are used to deliver optimized pupil through source mask optimization and evaluate OPC technology. DFM (Design For Manufacturing) related topics such as dummy metal insertion and design CD retarget are addressed together with critical design rules (e.g. Tip-to-Tip), to provide balanced design and patterning performance. Relevant wafer data are shown as a proof of above optimization process.
Design rule for advanced logic node is optimized together with EUV NXE 3400 wafer data and OPC performance. Imaging parameters such as SMO source, dose sensitivity, MEEF and other are considered in defining the pattern fidelity and associated design rules. In addition, positive tone development (PTD) process employing Dark Field (DF) EUV mask and negative tone development (NTD) process using Bright Field (BF) mask are included in the scope. Key differences between PTD and NTD process will be discussed from the perspective of fundamental imaging, OPC and lithography process. At last, stochastic effect will be evaluated on the key design rules such as tip- to-tip, tip-to-line, width/space etc.
As EUV lithography is getting ready for deployment in high volume manufacturing, lithography engineering focus moves to efficient computational lithography tools (mask correction, verification, source-, mask- and processoptimization) providing optimal RET solutions for EUV early design exploration. Key to computational lithography success is the prediction ability of the underlying lithography process simulation model. Topographic mask effects prediction is one of the major challenges with significant impact on both simulation quality of results and turn around time. In this paper, we apply a fast modeling approach to EUV light diffraction on topographic masks, which is based on fully rigorous topographic mask simulations. It is demonstrating performance benefits of several orders of magnitude while maintaining the accuracy requirements for productive cases. We explore its applicability to medium sized computational lithography tasks. The accurate mask solver results will be complemented with imaging and 3D resist simulations using the rigorous lithography simulator S-Litho by Synopsys.
This paper summarizes findings for an N5 equivalent M2 (pitch 32) layer patterned by means of SE EUV. Different mask tonalities and resist tonalities have been explored and a full patterning (litho plus etch) process into a BEOL stack has been developed. Resolution enhancement techniques like SRAFs insertion and retargeting have been evaluated and compared to a baseline clip just after OPC. Steps forward have been done to develop a full patterning process using SE EUV, being stochastics and variability the main items to address.
KEYWORDS: Optical lithography, Extreme ultraviolet, Metals, Logic, Manufacturing, Lithography, Back end of line, Extreme ultraviolet lithography, New and emerging technologies
In order to maintain the scaling trend in logic technology node progression, imec technology nodes started heavily utilizing design technology co-optimization (DTCO) on top of loosen pitch scaling trend to mitigate the burden from steep cost increase and yield challenge. Scaling boosters are adopted to enable DTCO process on top of patterning near its cliff to mitigate the cost increase. As the technology node further proceeds, DTCO also starts facing its cliff, and system technology co-optimization (STCO) is introduced to assist pitch and DTCO scaling to bridge 2-D IC technology to evolutionary technology options such as MRAM, 2.5-D heterogeneous integration, 3-D integration and 3-D IC. EUV is used to further assist pitch and DTCO scaling to maintain low cost with higher yield and faster turn-around-time (TAT). EUV single patterning, multiple patterning and high-NA EUV are considered on top of DTCO and STCO landscape to define imec technology nodes.
imec’s investigation on EUV single patterning insertion into industry 5nm-relevant logic metal layer is discussed. Achievement and challenge across imaging, OPC, mask data preparation and resulting wafer pattern fidelity are reported with a broad scope.
Best focus shift by mask 3D of isolated feature gets worse by the insertion of SRAF, which puts a negative impact on obtaining large overlap process window across features. imec’s effort across OPC including SMO and mask sizing is discussed with mask rule that affects mask writing. Resist stochastic induced defect is identified as a biggest challenge during the overall optimization, and options to overcome the challenge is investigated. For mask data preparation, dramatic increase in the data volume in EUV mask manufacturing is observed from iArF multiple patterning to EUV single patterning conversion, particularly by the insertion of SRAF. In addition, logic design consideration to make EUV single patterning more affordable compared to alternative patterning option is be discussed.
imec’s DTCO and EUV achievement toward imec 7nm (iN7) technology node which is industry 5nm node
equivalent is reported with a focus on cost and scaling. Patterning-aware design methodology supports both
iArF multiple patterning and EUV under one compliant design rule. FinFET device with contacted poly pitch of
42nm and metal pitch of 32nm with 7.5-track, 6.5-track, and 6-track standard cell library are explored. Scaling
boosters are used to provide additional scaling and die cost benefit while lessening pitch shrink burden, and it
makes EUV insertion more affordable. EUV pattern fidelity is optimized through OPC, SMO, M3D, mask
sizing and SRAF. Processed wafers were characterized and edge-placement-error (EPE) variability is validated
for EUV insertion. Scale-ability and cost of ownership of EUV patterning in aligned with iN7 standard cell
design, integration and patterning specification are discussed.
This paper summarizes findings on the iN7 platform (foundry N5 equivalent) for single exposure EUV (SE EUV) of M1 and M2 BEOL layers. Logic structures within these layers have been measured after litho and after etch, and variability was characterized both with conventional CD-SEM measurements as well as Hitachi contouring method. After analyzing the patterning of these layers, the impact of variability on potential interconnect reliability was studied by using MonteCarlo and process emulation simulations to determine if current litho/etch performance would meet success criteria for the given platform design rules.
The imec N7 (iN7) platform has been developed to evaluate EUV patterning of advanced logic BEOL layers. Its design is based on a 42 nm first-level metal (M1) pitch, and a 32 nm pitch for the subsequent metal layers1. With these pitches, the iN7 node is an ‘aggressive’ full-scaled N7, corresponding to IDM N7, or foundry N5.
Regarding the metal 2 layer, imec is evaluating two integration approaches: EUV single print and SAQP+EUV Block. Extensive work is reported on both approaches2,3. The work detailed in this paper will deal about the computational work done prior to tape-out for the EUV direct print option.
We will discuss the EUV source mask optimization for an ASML NXE:3300 EUV scanner. Afterwards we will shortly touch upon OPC compact modeling and more extensively on OPC itself. Based on the current design rules and MRC, printability checks indicate that only limited process windows are obtained. We propose ways to improve the printability through MRC and design. Applying those changes can potentially lead to a sufficient process window.
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